From: Jan Kiszka <jan.kiszka@siemens.com>
To: Andi Kleen <andi@firstfloor.org>
Cc: Huang Ying <ying.huang@intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@elte.hu>, Thomas Gleixner <tglx@linutronix.de>,
"H. Peter Anvin" <hpa@zytor.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: x86: Inconsistent xAPIC synchronization in arch_irq_work_raise?
Date: Thu, 23 Jan 2014 20:51:15 +0100 [thread overview]
Message-ID: <52E172B3.7080605@siemens.com> (raw)
In-Reply-To: <20140123192255.GB20765@two.firstfloor.org>
On 2014-01-23 20:22, Andi Kleen wrote:
>> So now I'm looking for consistent locking rules (which type of lock, who
>> is responsible when issuing IPIs?) and a good (ie. also efficient) way
>> to apply them.
>
> It has to be lockless, the machine checks run as NMIs.
> The whole point of the self nmi is to get back to a lockable state.
"It" is arch_irq_work_raise, or more?
arch_irq_work_raise looks consistent then, and we now know why there is
the trailing wait.
Remains the question if shorthand IPIs are always locked by their
callers. Some do (those in kernel/apic/io_apic.c e.g.), other seem to be
more relaxed with this (e.g. kernel/apic/hw_nmi.c or
native_send_call_func_single_ipi), unless I miss something again.
Jan
--
Siemens AG, Corporate Technology, CT RTC ITP SES-DE
Corporate Competence Center Embedded Linux
next prev parent reply other threads:[~2014-01-23 19:52 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-21 13:02 x86: Inconsistent xAPIC synchronization in arch_irq_work_raise? Jan Kiszka
2014-01-21 14:01 ` Peter Zijlstra
2014-01-21 14:10 ` Ingo Molnar
2014-01-21 14:11 ` Jan Kiszka
2014-01-21 14:34 ` Jan Kiszka
2014-01-21 14:51 ` Peter Zijlstra
2014-01-21 23:20 ` Huang Ying
2014-01-22 18:43 ` Andi Kleen
2014-01-23 18:51 ` Jan Kiszka
2014-01-23 19:11 ` Peter Zijlstra
2014-01-23 19:22 ` Andi Kleen
2014-01-23 19:51 ` Jan Kiszka [this message]
2014-01-23 20:17 ` Andi Kleen
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