From: Ben Dooks <ben.dooks@codethink.co.uk>
To: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/3] clk: rcar-h2: fix sd0/sd1 divisor table
Date: Fri, 07 Feb 2014 09:55:53 +0000 [thread overview]
Message-ID: <52F4ADA9.7020600@codethink.co.uk> (raw)
In-Reply-To: <87y51nbey3.wl%kuninori.morimoto.gx@gmail.com>
On 07/02/14 06:43, Kuninori Morimoto wrote:
> Hi William, Ben, Laurent
>
>>>>>>> static const struct clk_div_table cpg_sd01_div_table[] = {
>>>>>>> + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
>>>>>>> + { 4, 8 },
>>>>>>>
>>>>>>> { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
>>>>>>> { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
>
> According to HW team, datasheet is correct.
> Some HW has above un-documented implementation indeed,
> but these are not supported.
> But, 0x0100 (x1/8) on SD0FC/SD1FC is now supported and documented in
> latest datasheet.
Thanks, we do not have a copy of that so cannot comment.
>>>> sdhi0 showed 156MHz output, and it seemed to work. So there is a
>>>> distinct possibility that the sdh clock also supports setting 12
>>>> for a /10
>
> According to HW there,
> SDHFC will be stopped if you set 0xC.
We'll look at re-working this patch and getting it re-sent.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
WARNING: multiple messages have this Message-ID (diff)
From: ben.dooks@codethink.co.uk (Ben Dooks)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] clk: rcar-h2: fix sd0/sd1 divisor table
Date: Fri, 07 Feb 2014 09:55:53 +0000 [thread overview]
Message-ID: <52F4ADA9.7020600@codethink.co.uk> (raw)
In-Reply-To: <87y51nbey3.wl%kuninori.morimoto.gx@gmail.com>
On 07/02/14 06:43, Kuninori Morimoto wrote:
> Hi William, Ben, Laurent
>
>>>>>>> static const struct clk_div_table cpg_sd01_div_table[] = {
>>>>>>> + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
>>>>>>> + { 4, 8 },
>>>>>>>
>>>>>>> { 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
>>>>>>> { 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
>
> According to HW team, datasheet is correct.
> Some HW has above un-documented implementation indeed,
> but these are not supported.
> But, 0x0100 (x1/8) on SD0FC/SD1FC is now supported and documented in
> latest datasheet.
Thanks, we do not have a copy of that so cannot comment.
>>>> sdhi0 showed 156MHz output, and it seemed to work. So there is a
>>>> distinct possibility that the sdh clock also supports setting 12
>>>> for a /10
>
> According to HW there,
> SDHFC will be stopped if you set 0xC.
We'll look at re-working this patch and getting it re-sent.
--
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
next prev parent reply other threads:[~2014-02-07 9:55 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-04 18:17 Clock divisor/parent settings changes William Towle
2014-02-04 18:17 ` William Towle
2014-02-04 18:17 ` [PATCH 1/3] clk: rcar-h2: fix sd0/sd1 divisor table William Towle
2014-02-04 18:17 ` William Towle
2014-02-05 10:56 ` Laurent Pinchart
2014-02-05 10:56 ` Laurent Pinchart
2014-02-05 11:55 ` Ben Dooks
2014-02-05 11:55 ` Ben Dooks
2014-02-05 12:41 ` Ben Dooks
2014-02-05 12:41 ` Ben Dooks
2014-02-05 13:07 ` Laurent Pinchart
2014-02-05 13:07 ` Laurent Pinchart
2014-02-06 0:43 ` Kuninori Morimoto
2014-02-06 0:43 ` Kuninori Morimoto
2014-02-07 6:43 ` Kuninori Morimoto
2014-02-07 6:43 ` Kuninori Morimoto
2014-02-07 9:55 ` Ben Dooks [this message]
2014-02-07 9:55 ` Ben Dooks
2014-02-04 18:17 ` [PATCH 2/3] ARM: shmobile: r8a7790: specify multiple parents for cpg_clks William Towle
2014-02-04 18:17 ` William Towle
2014-02-05 9:15 ` [Linux-kernel] " Ben Dooks
2014-02-05 9:15 ` Ben Dooks
2014-02-05 10:32 ` Laurent Pinchart
2014-02-05 10:32 ` Laurent Pinchart
2014-02-05 10:36 ` Ben Dooks
2014-02-05 10:36 ` Ben Dooks
2014-02-05 10:57 ` Laurent Pinchart
2014-02-05 10:57 ` Laurent Pinchart
2014-02-04 18:17 ` [PATCH 3/3] clk: shmobile: handle multiple parent clocks for cpg clocks William Towle
2014-02-04 18:17 ` William Towle
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