* memory_barrier @ 2005-04-09 18:34 Bart De Schuymer 2005-04-09 19:28 ` memory_barrier Roland Dreier 0 siblings, 1 reply; 8+ messages in thread From: Bart De Schuymer @ 2005-04-09 18:34 UTC (permalink / raw) To: linux-kernel Hi, Is there any reason why __memory_barrier() is still referenced in the kernel source? grep -r memory_barrier gave the following back, which at first seems to suggest barrier() is defined using some phantom __memory_barrier(), quite deceiving... include/linux/compiler-intel.h:#define barrier() __memory_barrier() include/linux/compiler.h:# define barrier() __memory_barrier() include/asm-m32r/system.h: * memory_barrier() for examples and URLs to more information. include/asm-m32r/system.h: * memory_barrier(); include/asm-m32r/system.h: * memory_barrier(); include/asm-i386/system.h: * memory_barrier() for examples and URLs to more information. include/asm-i386/system.h: * memory_barrier(); include/asm-i386/system.h: * memory_barrier(); include/asm-mips/system.h: * memory_barrier() for examples and URLs to more information. include/asm-mips/system.h: * memory_barrier(); include/asm-mips/system.h: * memory_barrier(); include/asm-ia64/intel_intrin.h:void __memory_barrier(void); include/asm-ia64/intel_intrin.h:#define ia64_barrier() __memory_barrier() cheers, Bart ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: memory_barrier 2005-04-09 18:34 memory_barrier Bart De Schuymer @ 2005-04-09 19:28 ` Roland Dreier 0 siblings, 0 replies; 8+ messages in thread From: Roland Dreier @ 2005-04-09 19:28 UTC (permalink / raw) To: Bart De Schuymer; +Cc: linux-kernel Bart> Hi, Is there any reason why __memory_barrier() is still Bart> referenced in the kernel source? Bart> grep -r memory_barrier gave the following back, which at Bart> first seems to suggest barrier() is defined using some Bart> phantom __memory_barrier(), quite deceiving... Notice that it's used in <linux/compiler-intel.h> -- the Intel compiler has an intrinsic called __memory_barrier(). So the definition of barrier() using this intrinsic is entirely correct and appropriate. - R. ^ permalink raw reply [flat|nested] 8+ messages in thread
[parent not found: <CAGr+u+x0EFE+a424my7CqtBh449f=q0J_j=oGbyoKk4diUR2ng@mail.gmail.com>]
* Memory barrier [not found] <CAGr+u+x0EFE+a424my7CqtBh449f=q0J_j=oGbyoKk4diUR2ng@mail.gmail.com> @ 2011-12-09 7:24 ` trisha yad 2011-12-09 7:50 ` 卜弋天 0 siblings, 1 reply; 8+ messages in thread From: trisha yad @ 2011-12-09 7:24 UTC (permalink / raw) To: kernelnewbies Hi All, I need small clarification on memory barrier. #define smp_mb() ? ? ? ?mb() #define smp_rmb() ? ? ? rmb() #define smp_wmb() ? ? ? wmb() In case of SMP: is smp_mb() or smp_rmb() make order on current CPU or all cpu's Thanks ^ permalink raw reply [flat|nested] 8+ messages in thread
* Memory barrier 2011-12-09 7:24 ` Memory barrier trisha yad @ 2011-12-09 7:50 ` 卜弋天 2011-12-09 8:42 ` trisha yad 0 siblings, 1 reply; 8+ messages in thread From: 卜弋天 @ 2011-12-09 7:50 UTC (permalink / raw) To: kernelnewbies Hi : memory barriers can not make order on other cpus, only the current cpu's order will be promised. > Date: Fri, 9 Dec 2011 12:54:40 +0530 > Subject: Memory barrier > From: trisha1march at gmail.com > To: Kernelnewbies at kernelnewbies.org > > Hi All, > > I need small clarification on memory barrier. > #define smp_mb() mb() > #define smp_rmb() rmb() > #define smp_wmb() wmb() > In case of SMP: > is smp_mb() or smp_rmb() make order on current CPU or all cpu's > > Thanks > > _______________________________________________ > Kernelnewbies mailing list > Kernelnewbies at kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.kernelnewbies.org/pipermail/kernelnewbies/attachments/20111209/f9b9f997/attachment.html ^ permalink raw reply [flat|nested] 8+ messages in thread
* Memory barrier 2011-12-09 7:50 ` 卜弋天 @ 2011-12-09 8:42 ` trisha yad 2011-12-09 8:44 ` trisha yad 0 siblings, 1 reply; 8+ messages in thread From: trisha yad @ 2011-12-09 8:42 UTC (permalink / raw) To: kernelnewbies Thanks, I got bit confuse with below statement: This is from paper Memory access ordering Part 2 SMP conditional barriers The SMP conditional barriers are used to ensure a consistent view of memory between different cores within a cache coherent SMP system. When compiling a kernel without CONFIG_SMP, all SMP barriers are converted into plain compiler barriers. 2011/12/9 ??? <buyit@live.cn>: > Hi : > > memory barriers can not make order on other cpus, only the current > cpu's order will be promised. > > > >> Date: Fri, 9 Dec 2011 12:54:40 +0530 >> Subject: Memory barrier >> From: trisha1march at gmail.com >> To: Kernelnewbies at kernelnewbies.org > >> >> Hi All, >> >> I need small clarification on memory barrier. >> #define smp_mb() mb() >> #define smp_rmb() rmb() >> #define smp_wmb() wmb() >> In case of SMP: >> is smp_mb() or smp_rmb() make order on current CPU or all cpu's >> >> Thanks >> >> _______________________________________________ >> Kernelnewbies mailing list >> Kernelnewbies at kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ^ permalink raw reply [flat|nested] 8+ messages in thread
* Memory barrier 2011-12-09 8:42 ` trisha yad @ 2011-12-09 8:44 ` trisha yad 2011-12-09 10:07 ` 卜弋天 0 siblings, 1 reply; 8+ messages in thread From: trisha yad @ 2011-12-09 8:44 UTC (permalink / raw) To: kernelnewbies I will add more info here: smp_mb() Similar to mb(), but only guarantees ordering between cores/processors within an SMP system. All memory accesses before the smp_mb() will be visible to all cores within the SMP system before any accesses after the smp_mb(). smp_rmb() Like smp_mb(), but only guarantees ordering between read accesses. smp_wmb() Like smp_mb(), but only guarantees ordering between write accesses. So these made me total confuse . Thanks 2011/12/9 trisha yad <trisha1march@gmail.com>: > Thanks, > > I got bit confuse with below statement: > This is from paper Memory access ordering Part 2 > SMP conditional barriers > The SMP conditional barriers are used to ensure a consistent view of > memory between different cores within a cache coherent SMP system. > When compiling a kernel without CONFIG_SMP, all SMP barriers are > converted into plain compiler barriers. > > 2011/12/9 ??? <buyit@live.cn>: >> Hi : >> >> memory barriers can not make order on other cpus, only the current >> cpu's order will be promised. >> >> >> >>> Date: Fri, 9 Dec 2011 12:54:40 +0530 >>> Subject: Memory barrier >>> From: trisha1march at gmail.com >>> To: Kernelnewbies at kernelnewbies.org >> >>> >>> Hi All, >>> >>> I need small clarification on memory barrier. >>> #define smp_mb() mb() >>> #define smp_rmb() rmb() >>> #define smp_wmb() wmb() >>> In case of SMP: >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's >>> >>> Thanks >>> >>> _______________________________________________ >>> Kernelnewbies mailing list >>> Kernelnewbies at kernelnewbies.org >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ^ permalink raw reply [flat|nested] 8+ messages in thread
* Memory barrier 2011-12-09 8:44 ` trisha yad @ 2011-12-09 10:07 ` 卜弋天 2011-12-22 10:44 ` Vladimir Murzin 0 siblings, 1 reply; 8+ messages in thread From: 卜弋天 @ 2011-12-09 10:07 UTC (permalink / raw) To: kernelnewbies Hi : if you write code as below: golbal int in1=0,int2=0; cpu1: cpu2: int1 = 1; b= int2; smp_wmb() int2 = 2; a = in1; cpu2 may get the result: b==2 & a==0 , which means although cpu1 set int1=1 before int2=2, there is no garentee for cpu2 to perceive int1 before int2. you must add smp_rmb() inside cpu2 to prevent this. two cpus must cooperate to acheive the sequence memory order. > Date: Fri, 9 Dec 2011 14:14:37 +0530 > Subject: Re: Memory barrier > From: trisha1march at gmail.com > To: buyit at live.cn > CC: kernelnewbies at kernelnewbies.org > > I will add more info here: > smp_mb() > Similar to mb(), but only guarantees ordering between cores/processors > within an SMP system. All memory accesses before the smp_mb() will be > visible to all cores within the SMP system before any accesses after > the smp_mb(). > smp_rmb() > Like smp_mb(), but only guarantees ordering between read accesses. > smp_wmb() > Like smp_mb(), but only guarantees ordering between write accesses. > > So these made me total confuse . > > Thanks > > 2011/12/9 trisha yad <trisha1march@gmail.com>: > > Thanks, > > > > I got bit confuse with below statement: > > This is from paper Memory access ordering Part 2 > > SMP conditional barriers > > The SMP conditional barriers are used to ensure a consistent view of > > memory between different cores within a cache coherent SMP system. > > When compiling a kernel without CONFIG_SMP, all SMP barriers are > > converted into plain compiler barriers. > > > > 2011/12/9 ??? <buyit@live.cn>: > >> Hi : > >> > >> memory barriers can not make order on other cpus, only the current > >> cpu's order will be promised. > >> > >> > >> > >>> Date: Fri, 9 Dec 2011 12:54:40 +0530 > >>> Subject: Memory barrier > >>> From: trisha1march at gmail.com > >>> To: Kernelnewbies at kernelnewbies.org > >> > >>> > >>> Hi All, > >>> > >>> I need small clarification on memory barrier. > >>> #define smp_mb() mb() > >>> #define smp_rmb() rmb() > >>> #define smp_wmb() wmb() > >>> In case of SMP: > >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's > >>> > >>> Thanks > >>> > >>> _______________________________________________ > >>> Kernelnewbies mailing list > >>> Kernelnewbies at kernelnewbies.org > >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > _______________________________________________ > Kernelnewbies mailing list > Kernelnewbies at kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.kernelnewbies.org/pipermail/kernelnewbies/attachments/20111209/2eaf9339/attachment-0001.html ^ permalink raw reply [flat|nested] 8+ messages in thread
* Memory barrier 2011-12-09 10:07 ` 卜弋天 @ 2011-12-22 10:44 ` Vladimir Murzin 0 siblings, 0 replies; 8+ messages in thread From: Vladimir Murzin @ 2011-12-22 10:44 UTC (permalink / raw) To: kernelnewbies Hi, In my opinion it is not correct to say "make order on current CPU" in case of SMP. Actually, we cope with shared resource here - memory, and observes for that resource - CPUs. As soon as CPU is asked to make a barrier (with some sort of instruction) access to shared resource is ordered among all of observers. So, in case of SMP we have to protect shared resource with "hardware" memory barriers. In case of UP, memory is not shared, so, generally, we have to take care that memory access won't be optimized by compiler. P.S. Sorry for digging this thread. Best wishes Vladimir Murzin On 12/9/11, ??? <buyit@live.cn> wrote: > > Hi : > > if you write code as below: > > golbal int in1=0,int2=0; > > cpu1: cpu2: > > int1 = 1; b= int2; > smp_wmb() > int2 = 2; a = in1; > > cpu2 may get the result: b==2 & a==0 , which means although cpu1 set int1=1 > before int2=2, there is no garentee for cpu2 to perceive int1 before int2. > you must add smp_rmb() inside cpu2 to prevent this. > > two cpus must cooperate to acheive the sequence memory order. > > > > > >> Date: Fri, 9 Dec 2011 14:14:37 +0530 >> Subject: Re: Memory barrier >> From: trisha1march at gmail.com >> To: buyit at live.cn >> CC: kernelnewbies at kernelnewbies.org >> >> I will add more info here: >> smp_mb() >> Similar to mb(), but only guarantees ordering between cores/processors >> within an SMP system. All memory accesses before the smp_mb() will be >> visible to all cores within the SMP system before any accesses after >> the smp_mb(). >> smp_rmb() >> Like smp_mb(), but only guarantees ordering between read accesses. >> smp_wmb() >> Like smp_mb(), but only guarantees ordering between write accesses. >> >> So these made me total confuse . >> >> Thanks >> >> 2011/12/9 trisha yad <trisha1march@gmail.com>: >> > Thanks, >> > >> > I got bit confuse with below statement: >> > This is from paper Memory access ordering Part 2 >> > SMP conditional barriers >> > The SMP conditional barriers are used to ensure a consistent view of >> > memory between different cores within a cache coherent SMP system. >> > When compiling a kernel without CONFIG_SMP, all SMP barriers are >> > converted into plain compiler barriers. >> > >> > 2011/12/9 ??? <buyit@live.cn>: >> >> Hi : >> >> >> >> memory barriers can not make order on other cpus, only the current >> >> cpu's order will be promised. >> >> >> >> >> >> >> >>> Date: Fri, 9 Dec 2011 12:54:40 +0530 >> >>> Subject: Memory barrier >> >>> From: trisha1march at gmail.com >> >>> To: Kernelnewbies at kernelnewbies.org >> >> >> >>> >> >>> Hi All, >> >>> >> >>> I need small clarification on memory barrier. >> >>> #define smp_mb() mb() >> >>> #define smp_rmb() rmb() >> >>> #define smp_wmb() wmb() >> >>> In case of SMP: >> >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's >> >>> >> >>> Thanks >> >>> >> >>> _______________________________________________ >> >>> Kernelnewbies mailing list >> >>> Kernelnewbies at kernelnewbies.org >> >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> _______________________________________________ >> Kernelnewbies mailing list >> Kernelnewbies at kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ^ permalink raw reply [flat|nested] 8+ messages in thread
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2005-04-09 18:34 memory_barrier Bart De Schuymer
2005-04-09 19:28 ` memory_barrier Roland Dreier
[not found] <CAGr+u+x0EFE+a424my7CqtBh449f=q0J_j=oGbyoKk4diUR2ng@mail.gmail.com>
2011-12-09 7:24 ` Memory barrier trisha yad
2011-12-09 7:50 ` 卜弋天
2011-12-09 8:42 ` trisha yad
2011-12-09 8:44 ` trisha yad
2011-12-09 10:07 ` 卜弋天
2011-12-22 10:44 ` Vladimir Murzin
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