Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt

[Cedric Le Goater <clg@fr.ibm.com>]

On 02/20/2014 02:07 PM, Alexander Graf wrote:
> 
> On 20.02.2014, at 14:01, Cédric Le Goater <clg@fr.ibm.com> wrote:
> 
>> The latest glibc provides a memrchr routine using an extended opcode 
>> of the 'dcbt' instruction :
>>
>> 00000000000a7cc0 <memrchr>:
>>   a7cc0:       11 00 4c 3c     addis   r2,r12,17
>>   a7cc4:       b8 f8 42 38     addi    r2,r2,-1864
>>   a7cc8:       14 2a e3 7c     add     r7,r3,r5
>>   a7ccc:       d0 00 07 7c     neg     r0,r7
>>   a7cd0:       ff ff e7 38     addi    r7,r7,-1
>>   a7cd4:       78 1b 6a 7c     mr      r10,r3
>>   a7cd8:       24 06 e6 78     rldicr  r6,r7,0,56
>>   a7cdc:       60 00 20 39     li      r9,96
>>   a7ce0:       2c 32 09 7e     dcbtt   r9,r6
>>   ....
>>
>> which breaks grep, and other commands, in TCG mode :
>>
>>   invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0
>>
>> This patch adds the extended opcodes as no-ops just like the 'dcbt'
>> instruction. Other 'dcb*' instructions might be impacted but they 
>> have not showed up yet.
>>
>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
> 
> Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07 
> indicating that that bit should be reserved and I prefer to have those two 
> instructions be consistent with each other.

ok. I will send a v2.

Thanks,

C.