* [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
@ 2014-02-20 13:01 Cédric Le Goater
2014-02-20 13:07 ` Alexander Graf
0 siblings, 1 reply; 5+ messages in thread
From: Cédric Le Goater @ 2014-02-20 13:01 UTC (permalink / raw)
To: Alexander Graf; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
00000000000a7cc0 <memrchr>:
a7cc0: 11 00 4c 3c addis r2,r12,17
a7cc4: b8 f8 42 38 addi r2,r2,-1864
a7cc8: 14 2a e3 7c add r7,r3,r5
a7ccc: d0 00 07 7c neg r0,r7
a7cd0: ff ff e7 38 addi r7,r7,-1
a7cd4: 78 1b 6a 7c mr r10,r3
a7cd8: 24 06 e6 78 rldicr r6,r7,0,56
a7cdc: 60 00 20 39 li r9,96
a7ce0: 2c 32 09 7e dcbtt r9,r6
....
which breaks grep, and other commands, in TCG mode :
invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0
This patch adds the extended opcodes as no-ops just like the 'dcbt'
instruction. Other 'dcb*' instructions might be impacted but they
have not showed up yet.
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
target-ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 951f15e055d4..431358a83ac3 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9596,7 +9596,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
-GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
+GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
--
1.7.10.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
2014-02-20 13:01 [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt Cédric Le Goater
@ 2014-02-20 13:07 ` Alexander Graf
2014-02-20 13:09 ` Cedric Le Goater
2014-02-20 13:20 ` [Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst Cédric Le Goater
0 siblings, 2 replies; 5+ messages in thread
From: Alexander Graf @ 2014-02-20 13:07 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: list@suse.de:PowerPC, QEMU Developers
On 20.02.2014, at 14:01, Cédric Le Goater <clg@fr.ibm.com> wrote:
> The latest glibc provides a memrchr routine using an extended opcode
> of the 'dcbt' instruction :
>
> 00000000000a7cc0 <memrchr>:
> a7cc0: 11 00 4c 3c addis r2,r12,17
> a7cc4: b8 f8 42 38 addi r2,r2,-1864
> a7cc8: 14 2a e3 7c add r7,r3,r5
> a7ccc: d0 00 07 7c neg r0,r7
> a7cd0: ff ff e7 38 addi r7,r7,-1
> a7cd4: 78 1b 6a 7c mr r10,r3
> a7cd8: 24 06 e6 78 rldicr r6,r7,0,56
> a7cdc: 60 00 20 39 li r9,96
> a7ce0: 2c 32 09 7e dcbtt r9,r6
> ....
>
> which breaks grep, and other commands, in TCG mode :
>
> invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0
>
> This patch adds the extended opcodes as no-ops just like the 'dcbt'
> instruction. Other 'dcb*' instructions might be impacted but they
> have not showed up yet.
>
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07 indicating that that bit should be reserved and I prefer to have those two instructions be consistent with each other.
Alex
> ---
> target-ppc/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 951f15e055d4..431358a83ac3 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -9596,7 +9596,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
> GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
> GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
> GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
> -GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
> +GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
> GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
> GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
> GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
> --
> 1.7.10.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt
2014-02-20 13:07 ` Alexander Graf
@ 2014-02-20 13:09 ` Cedric Le Goater
2014-02-20 13:20 ` [Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst Cédric Le Goater
1 sibling, 0 replies; 5+ messages in thread
From: Cedric Le Goater @ 2014-02-20 13:09 UTC (permalink / raw)
To: Alexander Graf; +Cc: list@suse.de:PowerPC, QEMU Developers
On 02/20/2014 02:07 PM, Alexander Graf wrote:
>
> On 20.02.2014, at 14:01, Cédric Le Goater <clg@fr.ibm.com> wrote:
>
>> The latest glibc provides a memrchr routine using an extended opcode
>> of the 'dcbt' instruction :
>>
>> 00000000000a7cc0 <memrchr>:
>> a7cc0: 11 00 4c 3c addis r2,r12,17
>> a7cc4: b8 f8 42 38 addi r2,r2,-1864
>> a7cc8: 14 2a e3 7c add r7,r3,r5
>> a7ccc: d0 00 07 7c neg r0,r7
>> a7cd0: ff ff e7 38 addi r7,r7,-1
>> a7cd4: 78 1b 6a 7c mr r10,r3
>> a7cd8: 24 06 e6 78 rldicr r6,r7,0,56
>> a7cdc: 60 00 20 39 li r9,96
>> a7ce0: 2c 32 09 7e dcbtt r9,r6
>> ....
>>
>> which breaks grep, and other commands, in TCG mode :
>>
>> invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0
>>
>> This patch adds the extended opcodes as no-ops just like the 'dcbt'
>> instruction. Other 'dcb*' instructions might be impacted but they
>> have not showed up yet.
>>
>> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
>
> Please also remove the 0x02 bit from dcbtst. I don't see anything in 2.07
> indicating that that bit should be reserved and I prefer to have those two
> instructions be consistent with each other.
ok. I will send a v2.
Thanks,
C.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst
2014-02-20 13:07 ` Alexander Graf
2014-02-20 13:09 ` Cedric Le Goater
@ 2014-02-20 13:20 ` Cédric Le Goater
2014-02-20 13:23 ` Alexander Graf
1 sibling, 1 reply; 5+ messages in thread
From: Cédric Le Goater @ 2014-02-20 13:20 UTC (permalink / raw)
To: Alexander Graf; +Cc: Cédric Le Goater, qemu-ppc, qemu-devel
The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :
00000000000a7cc0 <memrchr>:
a7cc0: 11 00 4c 3c addis r2,r12,17
a7cc4: b8 f8 42 38 addi r2,r2,-1864
a7cc8: 14 2a e3 7c add r7,r3,r5
a7ccc: d0 00 07 7c neg r0,r7
a7cd0: ff ff e7 38 addi r7,r7,-1
a7cd4: 78 1b 6a 7c mr r10,r3
a7cd8: 24 06 e6 78 rldicr r6,r7,0,56
a7cdc: 60 00 20 39 li r9,96
a7ce0: 2c 32 09 7e dcbtt r9,r6
....
which breaks grep, and other commands, in TCG mode :
invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0
This patch adds the extended opcodes for dcbt/dcbtst as no-ops just
like the 'dcbt' instruction.
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
Changes in v2:
- added extended opcodes for dcbtst
target-ppc/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Index: qemu-agraf.git/target-ppc/translate.c
===================================================================
--- qemu-agraf.git.orig/target-ppc/translate.c
+++ qemu-agraf.git/target-ppc/translate.c
@@ -9596,8 +9596,8 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x0
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
-GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
-GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
+GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
+GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
--
1.7.10.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst
2014-02-20 13:20 ` [Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst Cédric Le Goater
@ 2014-02-20 13:23 ` Alexander Graf
0 siblings, 0 replies; 5+ messages in thread
From: Alexander Graf @ 2014-02-20 13:23 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: list@suse.de:PowerPC, QEMU Developers
On 20.02.2014, at 14:20, Cédric Le Goater <clg@fr.ibm.com> wrote:
> The latest glibc provides a memrchr routine using an extended opcode
> of the 'dcbt' instruction :
>
> 00000000000a7cc0 <memrchr>:
> a7cc0: 11 00 4c 3c addis r2,r12,17
> a7cc4: b8 f8 42 38 addi r2,r2,-1864
> a7cc8: 14 2a e3 7c add r7,r3,r5
> a7ccc: d0 00 07 7c neg r0,r7
> a7cd0: ff ff e7 38 addi r7,r7,-1
> a7cd4: 78 1b 6a 7c mr r10,r3
> a7cd8: 24 06 e6 78 rldicr r6,r7,0,56
> a7cdc: 60 00 20 39 li r9,96
> a7ce0: 2c 32 09 7e dcbtt r9,r6
> ....
>
> which breaks grep, and other commands, in TCG mode :
>
> invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0
>
> This patch adds the extended opcodes for dcbt/dcbtst as no-ops just
> like the 'dcbt' instruction.
>
> Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
Thanks, applied to ppc-next.
Alex
^ permalink raw reply [flat|nested] 5+ messages in thread
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2014-02-20 13:01 [Qemu-devel] [PATCH] target-ppc: add extended opcodes for dcbt Cédric Le Goater
2014-02-20 13:07 ` Alexander Graf
2014-02-20 13:09 ` Cedric Le Goater
2014-02-20 13:20 ` [Qemu-devel] [PATCH v2] target-ppc: add extended opcodes for dcbt/dcbtst Cédric Le Goater
2014-02-20 13:23 ` Alexander Graf
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