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From: Tomasz Figa <tomasz.figa@gmail.com>
To: linux-mmc@vger.kernel.org, Chris Ball <chris@printf.net>
Cc: linux-samsung-soc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Ben Dooks <ben-linux@fluff.org>,
	Jaehoon Chung <jh80.chung@samsung.com>,
	Seungwon Jeon <tgih.jun@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Andrew Morton <akpm@linux-foundation.org>
Subject: Re: [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management
Date: Mon, 03 Mar 2014 16:06:57 +0100	[thread overview]
Message-ID: <53149A91.4030509@gmail.com> (raw)
In-Reply-To: <530656D3.7010709@gmail.com>

On 20.02.2014 20:26, Tomasz Figa wrote:
> Hi Chris,
>
> On 07.02.2014 10:58, Tomasz Figa wrote:
>> Hi Chris,
>>
>> On 11.01.2014 22:39, Tomasz Figa wrote:
>>> On platforms prior to Exynos the SDHCI block used internal clock
>>> divider controlled by SELFREQ field of CLKCON register to divide base
>>> clock selected from several external clocks fed to the block by
>>> SELBASECLK bitfield of CONTROL2 register. Depending on wanted clock
>>> frequency, different external clock may be the best choice and so
>>> the driver needs to switch the SELBASECLK mux on the fly.
>>>
>>> However the selection logic has been broken for quite some time leaving
>>> the controller using always clock 0, which is not always the right
>>> source and leading to suboptimal performance of the SDHCI block on
>>> affected platforms.
>>>
>>> This series intends to fix the problems mentioned above and also
>>> clean-up
>>> clock management code slightly.
>>>
>>> Tested on S3C6410-based Mini6410 board, with following performance
>>> figures:
>>>
>>> * Before this series (133 MHz HCLK always selected, leading to at most
>>>    33 MHz card clock):
>>>
>>> root@tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  42 MB in  3.10 seconds =  13.54 MB/sec
>>> root@tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  44 MB in  3.11 seconds =  14.14 MB/sec
>>> root@tiny6410:~#
>>>
>>> * After this series (48 MHz EPLL clock selected, leading to 48 MHz card
>>>    clock):
>>>
>>> root@tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  56 MB in  3.04 seconds =  18.41 MB/sec
>>> root@tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  60 MB in  3.06 seconds =  19.63 MB/sec
>>> root@tiny6410:~#
>>>
>>> Tomasz Figa (6):
>>>    mmc: sdhci-s3c: Use shifts to divide by powers of two
>>>    mmc: sdhci-s3c: Cache bus clock rates
>>>    mmc: sdhci-s3c: Use correct condition to check for clock presence
>>>    mmc: sdhci-s3c: Simplify min/max clock calculation
>>>    mmc: sdhci-s3c: Fix handling of bus clock switching
>>>    mmc: sdhci-s3c: Do not allow frequencies higher than requested
>>>
>>>   drivers/mmc/host/sdhci-s3c.c | 170
>>> ++++++++++++++++++++-----------------------
>>>   1 file changed, 77 insertions(+), 93 deletions(-)
>>>
>>
>> What do you think about this series?
>
> Could you take this series for 3.15?

Ping.

It's been almost two months since I posted this series, it's been 
already ACKed and it would be nice to have it applied for upcoming release.

Best regards,
Tomasz

WARNING: multiple messages have this Message-ID (diff)
From: tomasz.figa@gmail.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management
Date: Mon, 03 Mar 2014 16:06:57 +0100	[thread overview]
Message-ID: <53149A91.4030509@gmail.com> (raw)
In-Reply-To: <530656D3.7010709@gmail.com>

On 20.02.2014 20:26, Tomasz Figa wrote:
> Hi Chris,
>
> On 07.02.2014 10:58, Tomasz Figa wrote:
>> Hi Chris,
>>
>> On 11.01.2014 22:39, Tomasz Figa wrote:
>>> On platforms prior to Exynos the SDHCI block used internal clock
>>> divider controlled by SELFREQ field of CLKCON register to divide base
>>> clock selected from several external clocks fed to the block by
>>> SELBASECLK bitfield of CONTROL2 register. Depending on wanted clock
>>> frequency, different external clock may be the best choice and so
>>> the driver needs to switch the SELBASECLK mux on the fly.
>>>
>>> However the selection logic has been broken for quite some time leaving
>>> the controller using always clock 0, which is not always the right
>>> source and leading to suboptimal performance of the SDHCI block on
>>> affected platforms.
>>>
>>> This series intends to fix the problems mentioned above and also
>>> clean-up
>>> clock management code slightly.
>>>
>>> Tested on S3C6410-based Mini6410 board, with following performance
>>> figures:
>>>
>>> * Before this series (133 MHz HCLK always selected, leading to at most
>>>    33 MHz card clock):
>>>
>>> root at tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  42 MB in  3.10 seconds =  13.54 MB/sec
>>> root at tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  44 MB in  3.11 seconds =  14.14 MB/sec
>>> root at tiny6410:~#
>>>
>>> * After this series (48 MHz EPLL clock selected, leading to 48 MHz card
>>>    clock):
>>>
>>> root at tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  56 MB in  3.04 seconds =  18.41 MB/sec
>>> root at tiny6410:~# hdparm -t /dev/mmcblk0
>>>
>>> /dev/mmcblk0:
>>>   Timing buffered disk reads:  60 MB in  3.06 seconds =  19.63 MB/sec
>>> root at tiny6410:~#
>>>
>>> Tomasz Figa (6):
>>>    mmc: sdhci-s3c: Use shifts to divide by powers of two
>>>    mmc: sdhci-s3c: Cache bus clock rates
>>>    mmc: sdhci-s3c: Use correct condition to check for clock presence
>>>    mmc: sdhci-s3c: Simplify min/max clock calculation
>>>    mmc: sdhci-s3c: Fix handling of bus clock switching
>>>    mmc: sdhci-s3c: Do not allow frequencies higher than requested
>>>
>>>   drivers/mmc/host/sdhci-s3c.c | 170
>>> ++++++++++++++++++++-----------------------
>>>   1 file changed, 77 insertions(+), 93 deletions(-)
>>>
>>
>> What do you think about this series?
>
> Could you take this series for 3.15?

Ping.

It's been almost two months since I posted this series, it's been 
already ACKed and it would be nice to have it applied for upcoming release.

Best regards,
Tomasz

  reply	other threads:[~2014-03-03 15:06 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-01-11 21:39 [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management Tomasz Figa
2014-01-11 21:39 ` Tomasz Figa
2014-01-11 21:39 ` [PATCH 1/6] mmc: sdhci-s3c: Use shifts to divide by powers of two Tomasz Figa
2014-01-11 21:39   ` Tomasz Figa
2014-01-11 21:39 ` [PATCH 2/6] mmc: sdhci-s3c: Cache bus clock rates Tomasz Figa
2014-01-11 21:39   ` Tomasz Figa
2014-01-11 21:39 ` [PATCH 3/6] mmc: sdhci-s3c: Use correct condition to check for clock presence Tomasz Figa
2014-01-11 21:39   ` Tomasz Figa
2014-01-11 21:39 ` [PATCH 4/6] mmc: sdhci-s3c: Simplify min/max clock calculation Tomasz Figa
2014-01-11 21:39   ` Tomasz Figa
2014-01-11 21:39 ` [PATCH 5/6] mmc: sdhci-s3c: Fix handling of bus clock switching Tomasz Figa
2014-01-11 21:39   ` Tomasz Figa
2014-01-11 21:39 ` [PATCH 6/6] mmc: sdhci-s3c: Do not allow frequencies higher than requested Tomasz Figa
2014-01-11 21:39   ` Tomasz Figa
2014-01-12 21:18 ` [PATCH 0/6] mmc: sdhci-s3c: Fix base clock source management Heiko Stübner
2014-01-12 21:18   ` Heiko Stübner
2014-01-13  5:47   ` Jaehoon Chung
2014-01-13  5:47     ` Jaehoon Chung
2014-01-13 12:43     ` Tomasz Figa
2014-01-13 12:43       ` Tomasz Figa
2014-02-07  9:58 ` Tomasz Figa
2014-02-07  9:58   ` Tomasz Figa
2014-02-20 19:26   ` Tomasz Figa
2014-02-20 19:26     ` Tomasz Figa
2014-03-03 15:06     ` Tomasz Figa [this message]
2014-03-03 15:06       ` Tomasz Figa
2014-03-03 15:24       ` Chris Ball
2014-03-03 15:24         ` Chris Ball
2014-03-03 15:25         ` Tomasz Figa
2014-03-03 15:25           ` Tomasz Figa

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