Re: [PATCH RFC v2 1/2] qspinlock: Introducing a 4-byte queue spinlock implementation

[Alexander Fyodorov <halcy@yandex.ru>]

29.08.2013, 19:25, "Waiman Long" <waiman.long@hp.com>:
> What I have been thinking is to set a flag in an architecture specific
> header file to tell if the architecture need a memory barrier. The
> generic code will then either do a smp_mb() or barrier() depending on
> the presence or absence of the flag. I would prefer to do more in the
> generic code, if possible.

If you use flag then you'll have to check it manually. It is better to add new smp_mb variant, I suggest calling it smp_mb_before_store(), and define it to barrier() on x86.

But the same constraints as to UNLOCK_LOCK_PREFIX should apply here, so it will be something like this:

arch/x86/include/asm/barrier.h:

+#if defined(CONFIG_X86_32) && \
+        (defined(CONFIG_X86_OOSTORE) || defined+(CONFIG_X86_PPRO_FENCE))
+/*      
+ * On PPro SMP or if we are using OOSTORE, we use a full memory barrier
+ * (PPro errata 66, 92)
+ */
+# define smp_mb_before_store() smp_mb()
+#else
+# define smp_mb_before_store() barrier()
+#endif