* EDAC PCIe errors when scannning the bus
@ 2014-03-19 12:46 Valentin Longchamp
2014-03-19 15:54 ` Johannes Thumshirn
2014-03-19 19:58 ` Rajat Jain
0 siblings, 2 replies; 6+ messages in thread
From: Valentin Longchamp @ 2014-03-19 12:46 UTC (permalink / raw)
To: linuxppc-dev@lists.ozlabs.org, linux-pci
[-- Attachment #1: Type: text/plain, Size: 2118 bytes --]
Hello,
We have a board that is based on Freescale's P2041 SoC. The boards has 2 PCIe
buses with this topology:
PCIe 0 <---> PEX8505 switch <---> 4 network devices
PCIE 2 <---> FPGA
On 3.10.33 + a subset of the Freescale SDK 1.4 patches, both PCIe buses work
well and we are able to use the devices on them.
For each bus, I however keep getting EDAC PCIe errors at the very first stage of
bus enumeration (please see the attached kernel log, with some debug output from
arch/powerpc/kernel/pci-common.c and drivers/pci/probe.c) for both buses.
My current "understanding" of the situation is such: since PCI_PROBE_NORMAL is
used, pcibios_scan_phb() calls pci_scan_child_bus() that does a pci_scan_slot()
on the bus for 32 slots. The first pci_scan_slot() is successful and it
discovers the P2041's PCIe Controller. All the 31 other pci_scan_slot() calls
generate an EDAC PCIe error, that is triggered by the configuration read
transaction to read an hypothetical vendor ID of a device on the bus. This is
relevant with that is reported by the EDAC error handler (all the 31 are the same):
> PCIE error(s) detected
> PCIE ERR_DR register: 0x00020000
ICCA bit is set: Access to an illegal configuration space from
PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected.
> PCIE ERR_CAP_STAT register: 0x80000001
To is set: Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
> PCIE ERR_CAP_R0 register: 0x00000800
FMT: 0b00, TYPE: 0b00100 (Config read I guess)
> PCIE ERR_CAP_R1 register: 0x00000000
> PCIE ERR_CAP_R2 register: 0x00000000
> PCIE ERR_CAP_R3 register: 0x00000000
Afterwards, pci_scan_child_bus() calls pcibios_fixup_bus (that maybe helps ?).
>From here, since the P2041's PCIe Controller is a bridge, pci_scan_bridge is
called for this bus and all the devices are detected without having any
configuration transaction causing EDAC errors.
Has someone already observed such a behavior ? Why do these initial transaction
generate an error ? What would be a possible fix to avoid these transaction
errors for these 31 (unneded ?) pci_scan_slot() calls on the initial bus ?
Best Regards,
Valentin
[-- Attachment #2: PCIe-boot-log.txt --]
[-- Type: text/plain, Size: 52105 bytes --]
U-Boot KM-v2013.10-7.0.5-00001-g29cfbaf (Mar 13 2014 - 11:40:15)
CPU0: P2041E, Version: 2.0, (0x82180120)
Core: e500mc, Version: 3.2, (0x80230032)
Clock Configuration:
CPU0:1333.333 MHz, CPU1:1333.333 MHz, CPU2:1333.333 MHz, CPU3:1333.333 MHz,
CCB:666.667 MHz,
DDR:533.333 MHz (1066.667 MT/s data rate) (Asynchronous), LBC:83.333 MHz
FMAN1: 533.333 MHz
QMAN: 333.333 MHz
PME: 333.333 MHz
L1: D-cache 32 KiB enabled
I-cache 32 KiB enabled
Reset Configuration Word (RCW):
00000000: 14600000 00000000 28200000 00000000
00000010: 148e70cf cfc02000 58000000 41000000
00000020: 00000000 00000000 00000000 f0428816
00000030: 00000000 00000000 00000000 00000000
Board: Keymile kmcoge4
I2C: ready
SPI: ready
DRAM: Initializing with SPD
Detected UDIMM
1 GiB (DDR3, 64-bit, CL=8, ECC off)
L2: 128 KiB enabled
Corenet Platform Cache: 1 MiB enabled
SERDES: bank 3 disabled
NAND: 256 MiB
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
PCIe FPGA config: done
PCIe1: Root Complex, x1, regs @ 0xfe200000
01:00.0 - 10b5:8505 - Bridge device
02:01.0 - 10b5:8505 - Bridge device
03:00.0 - 11ab:8000 - Network controller
02:02.0 - 10b5:8505 - Bridge device
04:00.0 - 11ab:8000 - Network controller
02:03.0 - 10b5:8505 - Bridge device
05:00.0 - 11ab:8000 - Network controller
02:04.0 - 10b5:8505 - Bridge device
06:00.0 - 11ab:8000 - Network controller
PCIe1: Bus 00 - 06
PCIe3: Root Complex, x1, regs @ 0xfe202000
08:00.0 - 10ee:000a - Memory controller
PCIe3: Bus 07 - 08
In: serial
Out: serial
Err: serial
Net: Initializing Fman
SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
Fman1: Uploading microcode version 106.1.9
FM1@DTSEC5 [PRIME]
Warning: Bootlimit (3) exceeded. Using altbootcmd.
Hit any key to stop autoboot: 0
Using FM1@DTSEC5 device
TFTP from server 192.168.12.201; our IP address is 192.168.12.16
Filename 'kmcoge4/kmcoge4.dtb'.
Load address: 0x1f80000
Loading: ###
119.1 KiB/s
done
Bytes transferred = 30240 (7620 hex)
Using FM1@DTSEC5 device
TFTP from server 192.168.12.201; our IP address is 192.168.12.16
Filename 'kmcoge4/ecc_bch_uImage'.
Load address: 0x1000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#############
4.4 MiB/s
done
Bytes transferred = 4002063 (3d110f hex)
WARNING: adjusting available memory to 30000000
## Booting kernel from Legacy Image at 01000000 ...
Image Name: Linux-3.10.32-kmcoge4-v0.5-00003
Image Type: PowerPC Linux Kernel Image (gzip compressed)
Data Size: 4001999 Bytes = 3.8 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 01f80000
Booting using the fdt blob at 0x1f80000
Uncompressing Kernel Image ... OK
Loading Device Tree to 03fe5000, end 03fff61f ... OK
Using Keymile kmp204x machine description
Memory CAM mapping: 256/256 Mb, residual: 510Mb
Initializing cgroup subsys cpu
Linux version 3.10.32-kmcoge4-v0.5-00003-g6885786-dirty (chlongv1@chber1-10533x.keymile.net) (gcc version 4.7.2 (GCC) ) #6 SMP Wed Mar 19 08:27:30 CET 2014
No /soc@ffe000000/qman@318000 property 'fsl,qman-fqd', using memblock_alloc(0000000000400000)
No /soc@ffe000000/qman@318000 property 'fsl,qman-pfdr', using memblock_alloc(0000000002000000)
Qman ver:0a01,01,02
No /soc@ffe000000/bman@31a000 property 'fsl,bman-fbpr', using memblock_alloc(0000000001000000)
Bman ver:0a02,01,00
Found legacy serial port 0 for /soc@ffe000000/serial@11c500
mem=ffe11c500, taddr=ffe11c500, irq=0, clk=333333330, speed=0
Found legacy serial port 1 for /soc@ffe000000/serial@11c600
mem=ffe11c600, taddr=ffe11c600, irq=0, clk=333333330, speed=0
Found legacy serial port 2 for /soc@ffe000000/serial@11d500
mem=ffe11d500, taddr=ffe11d500, irq=0, clk=333333330, speed=0
Found legacy serial port 3 for /soc@ffe000000/serial@11d600
mem=ffe11d600, taddr=ffe11d600, irq=0, clk=333333330, speed=0
CPU maps initialized for 1 thread per core
(thread shift is 0)
bootconsole [udbg0] enabled
setup_arch: bootmem
Keymile kmp204x board from Freescale Semiconductor
arch: exit
Top of RAM: 0x3fe7f000, Total RAM: 0x3fe7f000
Memory hole size: 0MB
Zone ranges:
DMA [mem 0x00000000-0x1fffffff]
Normal empty
HighMem [mem 0x20000000-0x3fe7efff]
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x00000000-0x3fe7efff]
On node 0 totalpages: 261759
free_area_init_node: node 0, pgdat c07f1ec0, node_mem_map c08bf000
DMA zone: 1024 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 131072 pages, LIFO batch:31
HighMem zone: 1021 pages used for memmap
HighMem zone: 130687 pages, LIFO batch:31
MMU: Allocated 1088 bytes of context maps for 255 contexts
PERCPU: Embedded 11 pages/cpu @c10c5000 s22400 r8192 d14464 u45056
pcpu-alloc: s22400 r8192 d14464 u45056 alloc=11*4096
pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260735
Kernel command line: root=/dev/nfs rw nfsroot=192.168.12.201:/opt/eldk/ppc_82xx debug ip=192.168.12.16:192.168.12.201:::kmcoge4:eth0:off: console=ttyS0,115200 mem=0x3fe7f000 init=/sbin/init-overlay.sh eccmode=bch phram.phram=phvar,0x3feff000,0x100000 ubi.mtd=ubi0,2048
forcing BCH ECC algorithm to: bch!
PID hash table entries: 2048 (order: 1, 8192 bytes)
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Sorting __ex_table...
High memory: 522744k
Memory: 909796k/1047036k available (7912k kernel code, 137240k reserved, 300k data, 732k bss, 324k init)
Kernel virtual memory layout:
* 0xfff5f000..0xfffff000 : fixmap
* 0xffc00000..0xffe00000 : highmem PTEs
* 0xffbfb000..0xffc00000 : early ioremap
* 0xe1000000..0xffbfb000 : vmalloc & ioremap
Hierarchical RCU implementation.
RCU debugfs-based tracing is enabled.
RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
NR_IRQS:512 nr_irqs:512 16
mpic: Setting up MPIC " OpenPIC " version 1.2 at ffe040000, max 4 CPUs
mpic: ISU size: 512, shift: 9, mask: 1ff
mpic: Initializing for 512 sources
time_init: decrementer frequency = 20.833333 MHz
time_init: processor frequency = 1333.333320 MHz
clocksource: timebase mult[3000000d] shift[24] registered
clockevent: decrementer mult[5555554] shift[32] cpu[0]
Console: colour dummy device 80x25
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
Initializing cgroup subsys net_cls
mpic: requesting IPIs...
e500 family performance monitor hardware support registered
Brought up 4 CPUs
devtmpfs: initialized
NET: Registered protocol family 16
Found FSL PCI host bridge at 0x0000000ffe200000. Firmware bus number: 0->6
PCI host bridge /pcie@ffe200000 (primary) ranges:
MEM 0x0000000c00000000..0x0000000c1fffffff -> 0x00000000e0000000
IO 0x0000000ff8000000..0x0000000ff800ffff -> 0x0000000000000000
/pcie@ffe200000: PCICSRBAR @ 0xdf000000
EDAC PCI0: Giving out device to module 'MPC85xx_edac' controller 'mpc85xx_pci_err': DEV 'ffe200000.pcie' (INTERRUPT)
MPC85xx_edac acquired irq 482 for PCI Err
MPC85xx_edac PCI err registered
Found FSL PCI host bridge at 0x0000000ffe202000. Firmware bus number: 0->1
PCI host bridge /pcie@ffe202000 ranges:
MEM 0x0000000c20000000..0x0000000c3fffffff -> 0x00000000e0000000
IO 0x0000000ff8010000..0x0000000ff801ffff -> 0x0000000000000000
/pcie@ffe202000: PCICSRBAR @ 0xdf000000
EDAC PCI1: Giving out device to module 'MPC85xx_edac' controller 'mpc85xx_pci_err': DEV 'ffe202000.pcie' (INTERRUPT)
MPC85xx_edac acquired irq 480 for PCI Err
MPC85xx_edac PCI err registered
PCI: Probing PCI hardware
PCI: Scanning PHB /pcie@ffe200000
PCI: PHB IO resource = 00000000-0000ffff [100] off 0x00000000
PCI: PHB MEM resource 0 = c00000000-c1fffffff [200] off 0xb20000000
fsl-pci ffe200000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
pci_bus 0000:00: root bus resource [mem 0xc00000000-0xc1fffffff] (bus address [0xe0000000-0xffffffff])
pci_bus 0000:00: root bus resource [bus 00-ff]
probe mode: 0
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff
pci_bus 0000:00: scanning bus
pci 0000:00:00.0: [1957:0412] type 01 class 0x0b2000
pci 0000:00:00.0: reg 10: [mem 0xdf000000-0xdfffffff]
PCI:0000:00:00.0 Resource 0 00000000df000000-00000000dfffffff [40200]
pci 0000:00:00.0: supports D1 D2
pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
pci_bus 0000:00: fixups for bus
PCI: Fixup bus devices 0 (PHB)
PCI: Try to map irq for 0000:00:00.0...
Got one, spec 4 cells (0x00000010 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 482
pci 0000:00:00.0: scanning [bus 01-06] behind bridge, pass 0
pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:01: scanning bus
pci 0000:01:00.0: [10b5:8505] type 01 class 0x060400
pci 0000:01:00.0: reg 10: [mem 0xc00000000-0xc0001ffff]
PCI:0000:01:00.0 Resource 0 0000000c00000000-0000000c0001ffff [40200]
pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
pci_bus 0000:01: fixups for bus
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
pci 0000:00:00.0: bridge window [mem 0xc00000000-0xc1fffffff]
PCI:0000:00:00.0 Bus rsrc 1 0000000c00000000-0000000c1fffffff [200]
PCI: Fixup bus devices 1 (0000:00:00.0)
PCI: Try to map irq for 0000:01:00.0...
Got one, spec 4 cells (0x00000028 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 40
pci 0000:01:00.0: scanning [bus 02-06] behind bridge, pass 0
pci 0000:01:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:02: scanning bus
pci 0000:02:01.0: [10b5:8505] type 01 class 0x060400
pci 0000:02:01.0: PME# supported from D0 D3hot D3cold
pci 0000:02:02.0: [10b5:8505] type 01 class 0x060400
pci 0000:02:02.0: PME# supported from D0 D3hot D3cold
pci 0000:02:03.0: [10b5:8505] type 01 class 0x060400
pci 0000:02:03.0: PME# supported from D0 D3hot D3cold
pci 0000:02:04.0: [10b5:8505] type 01 class 0x060400
pci 0000:02:04.0: PME# supported from D0 D3hot D3cold
pci_bus 0000:02: fixups for bus
pci 0000:01:00.0: PCI bridge to [bus 02-ff]
pci 0000:01:00.0: bridge window [mem 0xc00100000-0xc1fffffff]
PCI:0000:01:00.0 Bus rsrc 1 0000000c00100000-0000000c1fffffff [200]
PCI: Fixup bus devices 2 (0000:01:00.0)
PCI: Try to map irq for 0000:02:01.0...
Got one, spec 4 cells (0x00000001 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 20
PCI: Try to map irq for 0000:02:02.0...
Got one, spec 4 cells (0x00000002 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 21
PCI: Try to map irq for 0000:02:03.0...
Got one, spec 4 cells (0x00000003 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 22
PCI: Try to map irq for 0000:02:04.0...
Got one, spec 4 cells (0x00000028 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 40
pci 0000:02:01.0: scanning [bus 03-03] behind bridge, pass 0
pci 0000:02:02.0: scanning [bus 04-04] behind bridge, pass 0
pci 0000:02:03.0: scanning [bus 05-05] behind bridge, pass 0
pci 0000:02:04.0: scanning [bus 06-06] behind bridge, pass 0
pci 0000:02:01.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:03: scanning bus
pci 0000:03:00.0: [11ab:8000] type 00 class 0x020000
pci 0000:03:00.0: reg 10: [mem 0xc00100000-0xc001fffff 64bit pref]
pci 0000:03:00.0: reg 18: [mem 0xc04000000-0xc07ffffff 64bit pref]
PCI:0000:03:00.0 Resource 0 0000000c00100000-0000000c001fffff [14220c]
PCI:0000:03:00.0 Resource 2 0000000c04000000-0000000c07ffffff [14220c]
pci 0000:03:00.0: supports D1 D2
pci_bus 0000:03: fixups for bus
pci 0000:02:01.0: PCI bridge to [bus 03-ff]
pci 0000:02:01.0: bridge window [mem 0xc00100000-0xc07ffffff]
PCI:0000:02:01.0 Bus rsrc 1 0000000c00100000-0000000c07ffffff [200]
PCI: Fixup bus devices 3 (0000:02:01.0)
PCI: Try to map irq for 0000:03:00.0...
Got one, spec 4 cells (0x00000001 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 20
pci_bus 0000:03: bus scan returning with max=03
pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
pci 0000:02:02.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:04: scanning bus
pci 0000:04:00.0: [11ab:8000] type 00 class 0x020000
pci 0000:04:00.0: reg 10: [mem 0xc08000000-0xc080fffff 64bit pref]
pci 0000:04:00.0: reg 18: [mem 0xc0c000000-0xc0fffffff 64bit pref]
PCI:0000:04:00.0 Resource 0 0000000c08000000-0000000c080fffff [14220c]
PCI:0000:04:00.0 Resource 2 0000000c0c000000-0000000c0fffffff [14220c]
pci 0000:04:00.0: supports D1 D2
pci_bus 0000:04: fixups for bus
pci 0000:02:02.0: PCI bridge to [bus 04-ff]
pci 0000:02:02.0: bridge window [mem 0xc08000000-0xc0fffffff]
PCI:0000:02:02.0 Bus rsrc 1 0000000c08000000-0000000c0fffffff [200]
PCI: Fixup bus devices 4 (0000:02:02.0)
PCI: Try to map irq for 0000:04:00.0...
Got one, spec 4 cells (0x00000002 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 21
pci_bus 0000:04: bus scan returning with max=04
pci_bus 0000:04: busn_res: [bus 04-ff] end is updated to 04
pci 0000:02:03.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:05: scanning bus
pci 0000:05:00.0: [11ab:8000] type 00 class 0x020000
pci 0000:05:00.0: reg 10: [mem 0xc10000000-0xc100fffff 64bit pref]
pci 0000:05:00.0: reg 18: [mem 0xc14000000-0xc17ffffff 64bit pref]
PCI:0000:05:00.0 Resource 0 0000000c10000000-0000000c100fffff [14220c]
PCI:0000:05:00.0 Resource 2 0000000c14000000-0000000c17ffffff [14220c]
pci 0000:05:00.0: supports D1 D2
pci_bus 0000:05: fixups for bus
pci 0000:02:03.0: PCI bridge to [bus 05-ff]
pci 0000:02:03.0: bridge window [mem 0xc10000000-0xc17ffffff]
PCI:0000:02:03.0 Bus rsrc 1 0000000c10000000-0000000c17ffffff [200]
PCI: Fixup bus devices 5 (0000:02:03.0)
PCI: Try to map irq for 0000:05:00.0...
Got one, spec 4 cells (0x00000003 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 22
pci_bus 0000:05: bus scan returning with max=05
pci_bus 0000:05: busn_res: [bus 05-ff] end is updated to 05
pci 0000:02:04.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:06: scanning bus
pci 0000:06:00.0: [11ab:8000] type 00 class 0x020000
pci 0000:06:00.0: reg 10: [mem 0xc18000000-0xc180fffff 64bit pref]
pci 0000:06:00.0: reg 18: [mem 0xc1c000000-0xc1fffffff 64bit pref]
PCI:0000:06:00.0 Resource 0 0000000c18000000-0000000c180fffff [14220c]
PCI:0000:06:00.0 Resource 2 0000000c1c000000-0000000c1fffffff [14220c]
pci 0000:06:00.0: supports D1 D2
pci_bus 0000:06: fixups for bus
pci 0000:02:04.0: PCI bridge to [bus 06-ff]
pci 0000:02:04.0: bridge window [mem 0xc18000000-0xc1fffffff]
PCI:0000:02:04.0 Bus rsrc 1 0000000c18000000-0000000c1fffffff [200]
PCI: Fixup bus devices 6 (0000:02:04.0)
PCI: Try to map irq for 0000:06:00.0...
Got one, spec 4 cells (0x00000028 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 40
pci_bus 0000:06: bus scan returning with max=06
pci_bus 0000:06: busn_res: [bus 06-ff] end is updated to 06
pci_bus 0000:02: bus scan returning with max=06
pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 06
pci_bus 0000:01: bus scan returning with max=06
pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 06
pci_bus 0000:00: bus scan returning with max=06
pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 06
PCI: Scanning PHB /pcie@ffe202000
PCI: PHB IO resource = 00020000-0002ffff [100] off 0x00020000
PCI: PHB MEM resource 0 = c20000000-c3fffffff [200] off 0xb40000000
fsl-pci ffe202000.pcie: PCI host bridge to bus 0001:07
pci_bus 0001:07: root bus resource [io 0x20000-0x2ffff] (bus address [0x0000-0xffff])
pci_bus 0001:07: root bus resource [mem 0xc20000000-0xc3fffffff] (bus address [0xe0000000-0xffffffff])
pci_bus 0001:07: root bus resource [bus 07-ff]
probe mode: 0
pci_bus 0001:07: busn_res: [bus 07-ff] end is updated to ff
pci_bus 0001:07: scanning bus
pci 0001:07:00.0: [1957:0412] type 01 class 0x0b2000
pci 0001:07:00.0: reg 10: [mem 0xdf000000-0xdfffffff]
PCI:0001:07:00.0 Resource 0 00000000df000000-00000000dfffffff [40200]
pci 0001:07:00.0: supports D1 D2
pci 0001:07:00.0: PME# supported from D0 D1 D2 D3hot D3cold
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
PCIE error(s) detected
PCIE ERR_DR register: 0x00020000
PCIE ERR_CAP_STAT register: 0x80000001
PCIE ERR_CAP_R0 register: 0x00000800
PCIE ERR_CAP_R1 register: 0x00000000
PCIE ERR_CAP_R2 register: 0x00000000
PCIE ERR_CAP_R3 register: 0x00000000
pci_bus 0001:07: fixups for bus
PCI: Fixup bus devices 7 (PHB)
PCI: Try to map irq for 0001:07:00.0...
Got one, spec 4 cells (0x00000010 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 480
pci 0001:07:00.0: scanning [bus 01-01] behind bridge, pass 0
pci 0001:07:00.0: Primary bus is hard wired to 0
pci 0001:07:00.0: bridge configuration invalid ([bus 01-01]), reconfiguring
pci 0001:07:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0001:08: scanning bus
pci 0001:08:00.0: [10ee:000a] type 00 class 0x050000
pci 0001:08:00.0: reg 10: [mem 0xc20000000-0xc201fffff]
pci 0001:08:00.0: reg 14: [mem 0xc20200000-0xc203fffff]
PCI:0001:08:00.0 Resource 0 0000000c20000000-0000000c201fffff [40200]
PCI:0001:08:00.0 Resource 1 0000000c20200000-0000000c203fffff [40200]
pci 0001:08:00.0: supports D1 D2
pci 0001:08:00.0: PME# supported from D0 D1 D2 D3hot
pci_bus 0001:08: fixups for bus
pci 0001:07:00.0: PCI bridge to [bus 08-ff]
pci 0001:07:00.0: bridge window [mem 0xc20000000-0xc203fffff]
PCI:0001:07:00.0 Bus rsrc 1 0000000c20000000-0000000c203fffff [200]
PCI: Fixup bus devices 8 (0001:07:00.0)
PCI: Try to map irq for 0001:08:00.0...
Got one, spec 4 cells (0x0000002a 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 42
pci_bus 0001:08: bus scan returning with max=08
pci_bus 0001:08: busn_res: [bus 08-ff] end is updated to 08
pci_bus 0001:07: bus scan returning with max=08
pci_bus 0001:07: busn_res: [bus 07-ff] end is updated to 08
PCI: Allocating bus resources for 0000:00...
PCI: PHB (bus 0) bridge rsrc 4: 0000000000000000-000000000000ffff [0x100], parent c07bfa20 (PCI IO)
PCI: PHB (bus 0) bridge rsrc 5: 0000000c00000000-0000000c1fffffff [0x200], parent c07bf9f8 (PCI mem)
PCI: Allocating bus resources for 0000:01...
PCI: 0000:00:00.0 (bus 1) bridge rsrc 0: 0000000000000000-000000000000ffff [0x100], parent db14ae88 (/pcie@ffe200000)
PCI: 0000:00:00.0 (bus 1) bridge rsrc 1: 0000000c00000000-0000000c1fffffff [0x200], parent db14aeb0 (/pcie@ffe200000)
PCI: Allocating bus resources for 0000:02...
PCI: 0000:01:00.0 (bus 2) bridge rsrc 1: 0000000c00100000-0000000c1fffffff [0x200], parent db0ea698 (PCI Bus 0000:01)
PCI: Allocating bus resources for 0000:03...
PCI: 0000:02:01.0 (bus 3) bridge rsrc 1: 0000000c00100000-0000000c07ffffff [0x200], parent db0ea298 (PCI Bus 0000:02)
PCI: Allocating bus resources for 0000:04...
PCI: 0000:02:02.0 (bus 4) bridge rsrc 1: 0000000c08000000-0000000c0fffffff [0x200], parent db0ea298 (PCI Bus 0000:02)
PCI: Allocating bus resources for 0000:05...
PCI: 0000:02:03.0 (bus 5) bridge rsrc 1: 0000000c10000000-0000000c17ffffff [0x200], parent db0ea298 (PCI Bus 0000:02)
PCI: Allocating bus resources for 0000:06...
PCI: 0000:02:04.0 (bus 6) bridge rsrc 1: 0000000c18000000-0000000c1fffffff [0x200], parent db0ea298 (PCI Bus 0000:02)
PCI: Allocating bus resources for 0001:07...
PCI: PHB (bus 7) bridge rsrc 4: 0000000000020000-000000000002ffff [0x100], parent c07bfa20 (PCI IO)
PCI: PHB (bus 7) bridge rsrc 5: 0000000c20000000-0000000c3fffffff [0x200], parent c07bf9f8 (PCI mem)
PCI: Allocating bus resources for 0001:08...
PCI: 0001:07:00.0 (bus 8) bridge rsrc 0: 0000000000020000-000000000002ffff [0x100], parent db14a888 (/pcie@ffe202000)
PCI: 0001:07:00.0 (bus 8) bridge rsrc 1: 0000000c20000000-0000000c3fffffff [0x200], parent db14a8b0 (/pcie@ffe202000)
PCI: Allocating 0000:00:00.0: Resource 0: 00000000df000000..00000000dfffffff [40200]
PCI: Cannot allocate resource region 0 of device 0000:00:00.0, will remap
PCI: Allocating 0000:01:00.0: Resource 0: 0000000c00000000..0000000c0001ffff [40200]
PCI: Allocating 0000:03:00.0: Resource 0: 0000000c00100000..0000000c001fffff [14220c]
PCI: Allocating 0000:03:00.0: Resource 2: 0000000c04000000..0000000c07ffffff [14220c]
PCI: Allocating 0000:04:00.0: Resource 0: 0000000c08000000..0000000c080fffff [14220c]
PCI: Allocating 0000:04:00.0: Resource 2: 0000000c0c000000..0000000c0fffffff [14220c]
PCI: Allocating 0000:05:00.0: Resource 0: 0000000c10000000..0000000c100fffff [14220c]
PCI: Allocating 0000:05:00.0: Resource 2: 0000000c14000000..0000000c17ffffff [14220c]
PCI: Allocating 0000:06:00.0: Resource 0: 0000000c18000000..0000000c180fffff [14220c]
PCI: Allocating 0000:06:00.0: Resource 2: 0000000c1c000000..0000000c1fffffff [14220c]
PCI: Allocating 0001:07:00.0: Resource 0: 00000000df000000..00000000dfffffff [40200]
PCI: Cannot allocate resource region 0 of device 0001:07:00.0, will remap
PCI: Allocating 0001:08:00.0: Resource 0: 0000000c20000000..0000000c201fffff [40200]
PCI: Allocating 0001:08:00.0: Resource 1: 0000000c20200000..0000000c203fffff [40200]
Reserving legacy ranges for domain 0000
Candidate legacy IO: [io 0x0000-0x0fff]
PCI 0000:00 Cannot reserve Legacy IO [io 0x0000-0x0fff]
hose mem res: [mem 0xc00000000-0xc1fffffff]
Reserving legacy ranges for domain 0001
Candidate legacy IO: [io 0x20000-0x20fff]
PCI 0001:07 Cannot reserve Legacy IO [io 0x20000-0x20fff]
hose mem res: [mem 0xc20000000-0xc3fffffff]
PCI: Assigning unassigned resources...
pci 0000:02:01.0: bridge window [io 0x1000-0x0fff] to [bus 03] add_size 1000
pci 0000:02:01.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 03] add_size 200000
pci 0000:02:02.0: bridge window [io 0x1000-0x0fff] to [bus 04] add_size 1000
pci 0000:02:02.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 04] add_size 200000
pci 0000:02:03.0: bridge window [io 0x1000-0x0fff] to [bus 05] add_size 1000
pci 0000:02:03.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 05] add_size 200000
pci 0000:02:01.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pci 0000:02:02.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pci 0000:02:03.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pci 0000:01:00.0: bridge window [io 0x1000-0x0fff] to [bus 02-06] add_size 3000
pci 0000:02:01.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
pci 0000:02:02.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
pci 0000:02:03.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
pci 0000:01:00.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02-06] add_size 600000
pci 0000:01:00.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 600000
pci 0000:00:00.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 01-06] add_size 600000
pci 0000:00:00.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 600000
pci 0000:00:00.0: BAR 0: can't assign mem (size 0x1000000)
pci 0000:00:00.0: BAR 9: can't assign mem pref (size 0x600000)
pci 0000:00:00.0: BAR 0: can't assign mem (size 0x1000000)
pci 0000:00:00.0: BAR 9: can't assign mem pref (size 0x600000)
pci 0000:01:00.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 600000
pci 0000:01:00.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 3000
pci 0000:01:00.0: BAR 9: can't assign mem pref (size 0x600000)
pci 0000:01:00.0: BAR 7: assigned [io 0x1000-0x3fff]
pci 0000:01:00.0: BAR 9: can't assign mem pref (size 0x600000)
pci 0000:02:01.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
pci 0000:02:02.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
pci 0000:02:03.0: res[9]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000
pci 0000:02:01.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pci 0000:02:02.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pci 0000:02:03.0: res[7]=[io 0x1000-0x0fff] get_res_add_size add_size 1000
pci 0000:02:01.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:02:02.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:02:03.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:02:01.0: BAR 7: assigned [io 0x1000-0x1fff]
pci 0000:02:02.0: BAR 7: assigned [io 0x2000-0x2fff]
pci 0000:02:03.0: BAR 7: assigned [io 0x3000-0x3fff]
pci 0000:02:03.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:02:02.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:02:01.0: BAR 9: can't assign mem pref (size 0x200000)
pci 0000:02:01.0: PCI bridge to [bus 03]
pci 0000:02:01.0: bridge window [io 0x1000-0x1fff]
pci 0000:02:01.0: bridge window [mem 0xc00100000-0xc07ffffff]
pci 0000:02:02.0: PCI bridge to [bus 04]
pci 0000:02:02.0: bridge window [io 0x2000-0x2fff]
pci 0000:02:02.0: bridge window [mem 0xc08000000-0xc0fffffff]
pci 0000:02:03.0: PCI bridge to [bus 05]
pci 0000:02:03.0: bridge window [io 0x3000-0x3fff]
pci 0000:02:03.0: bridge window [mem 0xc10000000-0xc17ffffff]
pci 0000:02:04.0: PCI bridge to [bus 06]
pci 0000:02:04.0: bridge window [mem 0xc18000000-0xc1fffffff]
pci 0000:01:00.0: PCI bridge to [bus 02-06]
pci 0000:01:00.0: bridge window [io 0x1000-0x3fff]
pci 0000:01:00.0: bridge window [mem 0xc00100000-0xc1fffffff]
pci 0000:00:00.0: PCI bridge to [bus 01-06]
pci 0000:00:00.0: bridge window [io 0x0000-0xffff]
pci 0000:00:00.0: bridge window [mem 0xc00000000-0xc1fffffff]
pci 0001:07:00.0: BAR 0: can't assign mem (size 0x1000000)
pci 0001:07:00.0: PCI bridge to [bus 08]
pci 0001:07:00.0: bridge window [io 0x20000-0x2ffff]
pci 0001:07:00.0: bridge window [mem 0xc20000000-0xc3fffffff]
Some PCI device resources are unassigned, try booting with pci=realloc
PCI: Try to map irq for 0000:00:00.0...
Got one, spec 4 cells (0x00000010 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 482
PCI: Try to map irq for 0000:01:00.0...
Got one, spec 4 cells (0x00000028 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 40
PCI: Try to map irq for 0000:02:01.0...
Got one, spec 4 cells (0x00000001 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 20
PCI: Try to map irq for 0000:02:02.0...
Got one, spec 4 cells (0x00000002 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 21
PCI: Try to map irq for 0000:02:03.0...
Got one, spec 4 cells (0x00000003 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 22
PCI: Try to map irq for 0000:02:04.0...
Got one, spec 4 cells (0x00000028 0x00000001...) on /soc@ffe000000/pic@40000
Mapped to linux irq 40
PCI: Try to map irq for 0001:07:00.0...
Got one, spec 4 cells (0x00000010 0x00000002...) on /soc@ffe000000/pic@40000
Mapped to linux irq 480
pci_bus 0000:00: resource 4 [io 0x0000-0xffff]
pci_bus 0000:00: resource 5 [mem 0xc00000000-0xc1fffffff]
pci_bus 0000:01: resource 0 [io 0x0000-0xffff]
pci_bus 0000:01: resource 1 [mem 0xc00000000-0xc1fffffff]
pci_bus 0000:02: resource 0 [io 0x1000-0x3fff]
pci_bus 0000:02: resource 1 [mem 0xc00100000-0xc1fffffff]
pci_bus 0000:03: resource 0 [io 0x1000-0x1fff]
pci_bus 0000:03: resource 1 [mem 0xc00100000-0xc07ffffff]
pci_bus 0000:04: resource 0 [io 0x2000-0x2fff]
pci_bus 0000:04: resource 1 [mem 0xc08000000-0xc0fffffff]
pci_bus 0000:05: resource 0 [io 0x3000-0x3fff]
pci_bus 0000:05: resource 1 [mem 0xc10000000-0xc17ffffff]
pci_bus 0000:06: resource 1 [mem 0xc18000000-0xc1fffffff]
pci_bus 0001:07: resource 4 [io 0x20000-0x2ffff]
pci_bus 0001:07: resource 5 [mem 0xc20000000-0xc3fffffff]
pci_bus 0001:08: resource 0 [io 0x20000-0x2ffff]
pci_bus 0001:08: resource 1 [mem 0xc20000000-0xc3fffffff]
Setting up Freescale MSI support
Setting up Freescale MSI support
Setting up Freescale MSI support
bio: create slab <bio-0> at 0
vgaarb: loaded
SCSI subsystem initialized
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Bman err interrupt handler present
Bman portal initialised, cpu 0
Bman portal initialised, cpu 1
Bman portal initialised, cpu 2
Bman portal initialised, cpu 3
Bman portals initialised
Bman: BPID allocator includes range 32:32
Qman err interrupt handler present
Qman portal initialised, cpu 0
Qman portal initialised, cpu 1
Qman portal initialised, cpu 2
Qman portal initialised, cpu 3
Qman portals initialised
Qman: FQID allocator includes range 256:256
Qman: FQID allocator includes range 32768:32768
Qman: CGRID allocator includes range 0:256
Qman: pool channel allocator includes range 33:15
Switching to clocksource timebase
NET: Registered protocol family 2
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP: reno registered
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
PCI: CLS 32 bytes, default 64
audit: initializing netlink socket (disabled)
type=2000 audit(2.215:1): initialized
bounce pool size: 64 pages
HugeTLB registered 4 MB page size, pre-allocated 0 pages
HugeTLB registered 16 MB page size, pre-allocated 0 pages
HugeTLB registered 64 MB page size, pre-allocated 0 pages
HugeTLB registered 256 MB page size, pre-allocated 0 pages
HugeTLB registered 1 GB page size, pre-allocated 0 pages
squashfs: version 4.0 (2009/01/31) Phillip Lougher
NFS: Registering the id_resolver key type
Key type id_resolver registered
Key type id_legacy registered
NTFS driver 2.1.30 [Flags: R/O].
jffs2: version 2.2. (NAND) © 2001-2006 Red Hat, Inc.
aufs 3.10
msgmni has been set to 884
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
serial8250.0: ttyS0 at MMIO 0xffe11c500 (irq = 36) is a 16550A
console [ttyS0] enabled, bootconsole disabled
console [ttyS0] enabled, bootconsole disabled
serial8250.0: ttyS1 at MMIO 0xffe11c600 (irq = 36) is a 16550A
serial8250.0: ttyS2 at MMIO 0xffe11d500 (irq = 37) is a 16550A
serial8250.0: ttyS3 at MMIO 0xffe11d600 (irq = 37) is a 16550A
ePAPR hypervisor byte channel driver
Generic non-volatile memory driver v1.1
brd: module loaded
loop: module loaded
st: Version 20101219, fixed bufsize 32768, s/g segs 256
phram_setup name=phvar, addr=3feff000, len=1024k
phram: phvar device: 0x100000 at 0x3feff000
ONFI param page 0 valid
ONFI flash detected
NAND device: Manufacturer ID: 0x2c, Chip ID: 0xda (Micron MT29F2G08ABAEAWP), 256MiB, page size: 2048, OOB size: 64
forcing BCH ECC algorithm to 5!
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
1 ofpart partitions found on MTD device ffa00000.flash
Creating 1 MTD partitions on "ffa00000.flash":
0x000000000000-0x000010000000 : "ubi0"
eLBC NAND device at 0xfffa00000, bank 0
fsl_espi ffe110000.spi: master is unqueued, this is deprecated
m25p80 spi32766.0: s25fl256s1 (32768 Kbytes)
4 ofpart partitions found on MTD device spi32766.0
Creating 4 MTD partitions on "spi32766.0":
0x000000000000-0x000000100000 : "u-boot"
0x000000100000-0x000000110000 : "env"
0x000000110000-0x000000120000 : "envred"
0x000000120000-0x000000130000 : "fman-ucode"
m25p80 spi32766.2: m25p32 (4096 Kbytes)
1 ofpart partitions found on MTD device spi32766.2
Creating 1 MTD partitions on "spi32766.2":
0x000000000000-0x000000400000 : "fpga-config"
fsl_espi ffe110000.spi: at 0xe1106000 (irq = 53)
libphy: Fixed MDIO Bus: probed
fsl-pq_mdio ffe4e1120.mdio: deferring probe since network devices not present yet
platform ffe4e1120.mdio: Driver fsl-pq_mdio requests probe deferral
libphy: Freescale XGMAC MDIO Bus: probed
FMAN(0) Fifo size settings:
- Total buffers available(512 - 256B/buffer)
- Total throughput(3Gbps)
- Max frame size(1522B)
- 1G ports TX 3(12 bufs set (min: 12))
- 1G ports RX 3(142 bufs set (min: 14))
- OH-HC ports 4(8)
- Shared extra buffers(16)
FMAN(0) open dma settings:
- Total open dma available(32)
- 1G ports TX 3(4)
- 1G ports RX 3(4)
- OH-HC ports 4(1)
- Shared extra open dma(4)
FMAN(0) Tnums settings:
- Total Tnums available(128)
- 1G ports TX 3(19)
- 1G ports RX 3(20)
- OH-HC ports 4(2)
- Shared extra tnums(3)
Freescale FM module (Mar 18 2014:15:06:49), FMD API version 21.1.0
Freescale FM Ports module (Mar 18 2014:15:06:50)
dpaa_debugfs: FSL DPAA Ethernet debugfs entries ()
fsl_mac: mac.c:417:mac_load() fsl_mac: FSL FMan MAC API based driver ()
fsl_mac ffe4e0000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e0000.ethernet: FMan MAC address: 00:11:22:33:44:55
fsl_mac ffe4e2000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e2000.ethernet: FMan MAC address: 00:11:22:33:44:55
fsl_mac ffe4e8000.ethernet: FMan dTSEC version: 0x08240101
fsl_mac ffe4e8000.ethernet: FMan MAC address: 00:e0:df:a3:45:a1
fsl_dpa: dpaa_eth.c:4320:dpa_load() fsl_dpa: FSL DPAA Ethernet driver ()
fsl_dpa ethernet.16: Using private BM buffer pools
fsl_dpa: dpaa_eth.c:3715:dpa_rx_fq_init() Using dynamic RX QM frame queues
fsl_dpa: dpaa_eth.c:3739:dpa_tx_fq_init() Using dynamic TX QM frame queues
fsl_dpa ethernet.17: Using private BM buffer pools
fsl_dpa: dpaa_eth.c:3715:dpa_rx_fq_init() Using dynamic RX QM frame queues
fsl_dpa: dpaa_eth.c:3739:dpa_tx_fq_init() Using dynamic TX QM frame queues
fsl_dpa ethernet.18: Using private BM buffer pools
fsl_dpa: dpaa_eth.c:3715:dpa_rx_fq_init() Using dynamic RX QM frame queues
fsl_dpa: dpaa_eth.c:3739:dpa_tx_fq_init() Using dynamic TX QM frame queues
fsl_oh: offline_port.c:439:oh_port_load() fsl_oh: FSL FMan Offline Parsing port driver ()
i2c /dev entries driver
mpc-i2c ffe118000.i2c: timeout 1000000 us
mpc-i2c ffe118000.i2c: SCL GPIO pin not yet available, deferring probing
mpc-i2c ffe118000.i2c: failed to request GPIOs
platform ffe118000.i2c: Driver mpc-i2c requests probe deferral
Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software
mpc85xx_mc_err_probe: No ECC DIMMs discovered
caam ffe300000.crypto: device ID = 0x0a12010000000000 (Era 3)
caam ffe300000.crypto: job rings = 4, qi = 1
caam ffe300000.crypto: fsl,sec-v4.2 algorithms registered in /proc/crypto
platform ffe301000.jr: registering rng-caam
qriox ffb000000.bec: GPIO ctlr registered
qriox ffb000000.bec: GPIO export registered
qriox ffb000000.bec: IRQ ctlr registered
qriox ffb000000.bec: QRIO1 Rev. 0x13 registered @ 0xffb000000..0xffb00007f, BUF_ENA=ON
qriox ffb000000.bec: Populate qriox child nodes...
bc_get_addr: bc_get_addr no node, trying compatible node
created "/proc/driver/bootcount"
bootcount driver registered.
bfticu: attaching bftic4, private db461940
bfticu: physical resources [mem 0xfe0000000-0xfe00000ff]
bfticu fe0000000.bftic4: Chip id correct 0x65
bfticu fe0000000.bftic4: Set up succesfully 48 bfticu_irqs
bfticu:init
km_event_probe: probing events for qrio_events.12
km_event_handler: setup OK.
km_event_probe: probing events for fe0000000.bftic4_events
km_event_handler: setup OK.
u32 classifier
Performance counters on
ipip: IPv4 over IPv4 tunneling driver
TCP: cubic registered
Initializing XFRM netlink socket
NET: Registered protocol family 10
sit: IPv6 over IPv4 tunneling driver
NET: Registered protocol family 17
NET: Registered protocol family 15
tipc: Activated (version 2.0.0)
NET: Registered protocol family 30
tipc: Started in single node mode
Key type dns_resolver registered
libphy: Freescale PowerQUICC MII Bus: probed
mpc-i2c ffe118000.i2c: timeout 1000000 us
mpc-i2c ffe118000.i2c: requested GPIO 180 for SCL
mpc-i2c ffe118000.i2c: requested GPIO 181 for SDA
UBI: attaching mtd1 to ubi0
UBI: scanning is finished
UBI: attached mtd1 (name "ubi0", size 256 MiB) to ubi0
UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 512
UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
UBI: good PEBs: 2044, bad PEBs: 4, corrupted PEBs: 0
UBI: user volume: 11, internal volumes: 1, max. volumes count: 128
UBI: max/mean erase counter: 2/0, WL threshold: 4096, image sequence number: 0
UBI: available PEBs: 1017, total reserved PEBs: 1027, PEBs reserved for bad PEB handling: 36
UBI: background thread "ubi_bgt0d" started, PID 110
drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
IP-Config: Guessing netmask 255.255.255.0
IP-Config: Complete:
device=eth0, hwaddr=00:e0:df:a3:45:a1, ipaddr=192.168.12.16, mask=255.255.255.0, gw=255.255.255.255
host=kmcoge4, domain=, nis-domain=(none)
bootserver=192.168.12.201, rootserver=192.168.12.201, rootpath=
VFS: Mounted root (nfs filesystem) on device 0:17.
devtmpfs: mounted
Freeing unused kernel memory: 324K (c0769000 - c07ba000)
6.677 INFO init-overlay done in 0.26
8.300 INFO sysinit done in 1.61
root@kmcoge4:~#
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: EDAC PCIe errors when scannning the bus
2014-03-19 12:46 EDAC PCIe errors when scannning the bus Valentin Longchamp
@ 2014-03-19 15:54 ` Johannes Thumshirn
2014-03-19 19:58 ` Rajat Jain
1 sibling, 0 replies; 6+ messages in thread
From: Johannes Thumshirn @ 2014-03-19 15:54 UTC (permalink / raw)
To: Valentin Longchamp; +Cc: linuxppc-dev@lists.ozlabs.org, linux-pci
On Wed, Mar 19, 2014 at 01:46:37PM +0100, Valentin Longchamp wrote:
> Hello,
>
> We have a board that is based on Freescale's P2041 SoC. The boards has 2 PCIe
> buses with this topology:
>
> PCIe 0 <---> PEX8505 switch <---> 4 network devices
> PCIE 2 <---> FPGA
>
> On 3.10.33 + a subset of the Freescale SDK 1.4 patches, both PCIe buses work
> well and we are able to use the devices on them.
>
> For each bus, I however keep getting EDAC PCIe errors at the very first stage of
> bus enumeration (please see the attached kernel log, with some debug output from
> arch/powerpc/kernel/pci-common.c and drivers/pci/probe.c) for both buses.
>
> My current "understanding" of the situation is such: since PCI_PROBE_NORMAL is
> used, pcibios_scan_phb() calls pci_scan_child_bus() that does a pci_scan_slot()
> on the bus for 32 slots. The first pci_scan_slot() is successful and it
> discovers the P2041's PCIe Controller. All the 31 other pci_scan_slot() calls
> generate an EDAC PCIe error, that is triggered by the configuration read
> transaction to read an hypothetical vendor ID of a device on the bus. This is
> relevant with that is reported by the EDAC error handler (all the 31 are the same):
>
> > PCIE error(s) detected
> > PCIE ERR_DR register: 0x00020000
>
> ICCA bit is set: Access to an illegal configuration space from
> PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected.
>
> > PCIE ERR_CAP_STAT register: 0x80000001
>
> To is set: Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
>
> > PCIE ERR_CAP_R0 register: 0x00000800
>
> FMT: 0b00, TYPE: 0b00100 (Config read I guess)
>
> > PCIE ERR_CAP_R1 register: 0x00000000
> > PCIE ERR_CAP_R2 register: 0x00000000
> > PCIE ERR_CAP_R3 register: 0x00000000
>
> Afterwards, pci_scan_child_bus() calls pcibios_fixup_bus (that maybe helps ?).
> From here, since the P2041's PCIe Controller is a bridge, pci_scan_bridge is
> called for this bus and all the devices are detected without having any
> configuration transaction causing EDAC errors.
>
> Has someone already observed such a behavior ? Why do these initial transaction
> generate an error ? What would be a possible fix to avoid these transaction
> errors for these 31 (unneded ?) pci_scan_slot() calls on the initial bus ?
>
> Best Regards,
>
> Valentin
Hi Valentin,
I've encountered similar problems on a P4080 based design (mine has additional
machine checks that cause an oops). I haven't solved it yet, so I unfortunately
can't offer you a fix. But I was told there are some errata workarounds that
more or less could have an impact on PCIe behavior. Could you show me the output
of U-Boot's errata command?
Especially if the workarounds for A-004580 and A-004849 are in place.
Johannes
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: EDAC PCIe errors when scannning the bus
@ 2014-03-19 15:54 ` Johannes Thumshirn
0 siblings, 0 replies; 6+ messages in thread
From: Johannes Thumshirn @ 2014-03-19 15:54 UTC (permalink / raw)
To: Valentin Longchamp; +Cc: linux-pci, linuxppc-dev@lists.ozlabs.org
On Wed, Mar 19, 2014 at 01:46:37PM +0100, Valentin Longchamp wrote:
> Hello,
>
> We have a board that is based on Freescale's P2041 SoC. The boards has 2 PCIe
> buses with this topology:
>
> PCIe 0 <---> PEX8505 switch <---> 4 network devices
> PCIE 2 <---> FPGA
>
> On 3.10.33 + a subset of the Freescale SDK 1.4 patches, both PCIe buses work
> well and we are able to use the devices on them.
>
> For each bus, I however keep getting EDAC PCIe errors at the very first stage of
> bus enumeration (please see the attached kernel log, with some debug output from
> arch/powerpc/kernel/pci-common.c and drivers/pci/probe.c) for both buses.
>
> My current "understanding" of the situation is such: since PCI_PROBE_NORMAL is
> used, pcibios_scan_phb() calls pci_scan_child_bus() that does a pci_scan_slot()
> on the bus for 32 slots. The first pci_scan_slot() is successful and it
> discovers the P2041's PCIe Controller. All the 31 other pci_scan_slot() calls
> generate an EDAC PCIe error, that is triggered by the configuration read
> transaction to read an hypothetical vendor ID of a device on the bus. This is
> relevant with that is reported by the EDAC error handler (all the 31 are the same):
>
> > PCIE error(s) detected
> > PCIE ERR_DR register: 0x00020000
>
> ICCA bit is set: Access to an illegal configuration space from
> PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected.
>
> > PCIE ERR_CAP_STAT register: 0x80000001
>
> To is set: Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
>
> > PCIE ERR_CAP_R0 register: 0x00000800
>
> FMT: 0b00, TYPE: 0b00100 (Config read I guess)
>
> > PCIE ERR_CAP_R1 register: 0x00000000
> > PCIE ERR_CAP_R2 register: 0x00000000
> > PCIE ERR_CAP_R3 register: 0x00000000
>
> Afterwards, pci_scan_child_bus() calls pcibios_fixup_bus (that maybe helps ?).
> From here, since the P2041's PCIe Controller is a bridge, pci_scan_bridge is
> called for this bus and all the devices are detected without having any
> configuration transaction causing EDAC errors.
>
> Has someone already observed such a behavior ? Why do these initial transaction
> generate an error ? What would be a possible fix to avoid these transaction
> errors for these 31 (unneded ?) pci_scan_slot() calls on the initial bus ?
>
> Best Regards,
>
> Valentin
Hi Valentin,
I've encountered similar problems on a P4080 based design (mine has additional
machine checks that cause an oops). I haven't solved it yet, so I unfortunately
can't offer you a fix. But I was told there are some errata workarounds that
more or less could have an impact on PCIe behavior. Could you show me the output
of U-Boot's errata command?
Especially if the workarounds for A-004580 and A-004849 are in place.
Johannes
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: EDAC PCIe errors when scannning the bus
2014-03-19 12:46 EDAC PCIe errors when scannning the bus Valentin Longchamp
2014-03-19 15:54 ` Johannes Thumshirn
@ 2014-03-19 19:58 ` Rajat Jain
1 sibling, 0 replies; 6+ messages in thread
From: Rajat Jain @ 2014-03-19 19:58 UTC (permalink / raw)
To: Valentin Longchamp, linuxppc-dev@lists.ozlabs.org,
linux-pci@vger.kernel.org
Cc: Guenter Roeck
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: EDAC PCIe errors when scannning the bus
2014-03-19 15:54 ` Johannes Thumshirn
@ 2014-03-20 10:44 ` Valentin Longchamp
-1 siblings, 0 replies; 6+ messages in thread
From: Valentin Longchamp @ 2014-03-20 10:44 UTC (permalink / raw)
To: Johannes Thumshirn
Cc: linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org
Hello Johannes,
On 03/19/2014 04:54 PM, Johannes Thumshirn wrote:
> On Wed, Mar 19, 2014 at 01:46:37PM +0100, Valentin Longchamp wrote:
>> Hello,
>>
>> We have a board that is based on Freescale's P2041 SoC. The boards has 2 PCIe
>> buses with this topology:
>>
>> PCIe 0 <---> PEX8505 switch <---> 4 network devices
>> PCIE 2 <---> FPGA
>>
>> On 3.10.33 + a subset of the Freescale SDK 1.4 patches, both PCIe buses work
>> well and we are able to use the devices on them.
>>
>> For each bus, I however keep getting EDAC PCIe errors at the very first stage of
>> bus enumeration (please see the attached kernel log, with some debug output from
>> arch/powerpc/kernel/pci-common.c and drivers/pci/probe.c) for both buses.
>>
>> My current "understanding" of the situation is such: since PCI_PROBE_NORMAL is
>> used, pcibios_scan_phb() calls pci_scan_child_bus() that does a pci_scan_slot()
>> on the bus for 32 slots. The first pci_scan_slot() is successful and it
>> discovers the P2041's PCIe Controller. All the 31 other pci_scan_slot() calls
>> generate an EDAC PCIe error, that is triggered by the configuration read
>> transaction to read an hypothetical vendor ID of a device on the bus. This is
>> relevant with that is reported by the EDAC error handler (all the 31 are the same):
>>
>>> PCIE error(s) detected
>>> PCIE ERR_DR register: 0x00020000
>>
>> ICCA bit is set: Access to an illegal configuration space from
>> PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected.
>>
>>> PCIE ERR_CAP_STAT register: 0x80000001
>>
>> To is set: Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
>>
>>> PCIE ERR_CAP_R0 register: 0x00000800
>>
>> FMT: 0b00, TYPE: 0b00100 (Config read I guess)
>>
>>> PCIE ERR_CAP_R1 register: 0x00000000
>>> PCIE ERR_CAP_R2 register: 0x00000000
>>> PCIE ERR_CAP_R3 register: 0x00000000
>>
>> Afterwards, pci_scan_child_bus() calls pcibios_fixup_bus (that maybe helps ?).
>> From here, since the P2041's PCIe Controller is a bridge, pci_scan_bridge is
>> called for this bus and all the devices are detected without having any
>> configuration transaction causing EDAC errors.
>>
>> Has someone already observed such a behavior ? Why do these initial transaction
>> generate an error ? What would be a possible fix to avoid these transaction
>> errors for these 31 (unneded ?) pci_scan_slot() calls on the initial bus ?
>>
>
> I've encountered similar problems on a P4080 based design (mine has additional
> machine checks that cause an oops). I haven't solved it yet, so I unfortunately
> can't offer you a fix. But I was told there are some errata workarounds that
> more or less could have an impact on PCIe behavior. Could you show me the output
> of U-Boot's errata command?
Here is the output for the errata command:
> => errata
> Work-around for Erratum CPU-A003999 enabled
> Work-around for Erratum DDR-A003473 enabled
> Work-around for Erratum ESDHC111 enabled
> Work-around for Erratum DDR-A003 enabled
> Work-around for Erratum A004510 enabled
> Work-around for Erratum SRIO-A004034 enabled
> Work-around for Erratum A004849 is not enabled
> Work-around for Erratum A004580 is not enabled
> Work-around for Erratum USB14 enabled
>
> Especially if the workarounds for A-004580 and A-004849 are in place.
>
So both are not enabled, I am going to fix that. Surprisingly, A-004580 is not
defined for the P2041 in u-boot even though it is also present in the P2041's
errata sheet, I had to enable it myself.
However, I expect that enabling the workarounds for these 2 Errata are good for
the system but it will not solve the PCIe EDAC problem.
Thank you for the input.
Valentin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: EDAC PCIe errors when scannning the bus
@ 2014-03-20 10:44 ` Valentin Longchamp
0 siblings, 0 replies; 6+ messages in thread
From: Valentin Longchamp @ 2014-03-20 10:44 UTC (permalink / raw)
To: Johannes Thumshirn
Cc: linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Hello Johannes,
On 03/19/2014 04:54 PM, Johannes Thumshirn wrote:
> On Wed, Mar 19, 2014 at 01:46:37PM +0100, Valentin Longchamp wrote:
>> Hello,
>>
>> We have a board that is based on Freescale's P2041 SoC. The boards has 2 PCIe
>> buses with this topology:
>>
>> PCIe 0 <---> PEX8505 switch <---> 4 network devices
>> PCIE 2 <---> FPGA
>>
>> On 3.10.33 + a subset of the Freescale SDK 1.4 patches, both PCIe buses work
>> well and we are able to use the devices on them.
>>
>> For each bus, I however keep getting EDAC PCIe errors at the very first stage of
>> bus enumeration (please see the attached kernel log, with some debug output from
>> arch/powerpc/kernel/pci-common.c and drivers/pci/probe.c) for both buses.
>>
>> My current "understanding" of the situation is such: since PCI_PROBE_NORMAL is
>> used, pcibios_scan_phb() calls pci_scan_child_bus() that does a pci_scan_slot()
>> on the bus for 32 slots. The first pci_scan_slot() is successful and it
>> discovers the P2041's PCIe Controller. All the 31 other pci_scan_slot() calls
>> generate an EDAC PCIe error, that is triggered by the configuration read
>> transaction to read an hypothetical vendor ID of a device on the bus. This is
>> relevant with that is reported by the EDAC error handler (all the 31 are the same):
>>
>>> PCIE error(s) detected
>>> PCIE ERR_DR register: 0x00020000
>>
>> ICCA bit is set: Access to an illegal configuration space from
>> PEX_CONFIG_ADDR/PEX_CONFIG_DATA was detected.
>>
>>> PCIE ERR_CAP_STAT register: 0x80000001
>>
>> To is set: Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
>>
>>> PCIE ERR_CAP_R0 register: 0x00000800
>>
>> FMT: 0b00, TYPE: 0b00100 (Config read I guess)
>>
>>> PCIE ERR_CAP_R1 register: 0x00000000
>>> PCIE ERR_CAP_R2 register: 0x00000000
>>> PCIE ERR_CAP_R3 register: 0x00000000
>>
>> Afterwards, pci_scan_child_bus() calls pcibios_fixup_bus (that maybe helps ?).
>> From here, since the P2041's PCIe Controller is a bridge, pci_scan_bridge is
>> called for this bus and all the devices are detected without having any
>> configuration transaction causing EDAC errors.
>>
>> Has someone already observed such a behavior ? Why do these initial transaction
>> generate an error ? What would be a possible fix to avoid these transaction
>> errors for these 31 (unneded ?) pci_scan_slot() calls on the initial bus ?
>>
>
> I've encountered similar problems on a P4080 based design (mine has additional
> machine checks that cause an oops). I haven't solved it yet, so I unfortunately
> can't offer you a fix. But I was told there are some errata workarounds that
> more or less could have an impact on PCIe behavior. Could you show me the output
> of U-Boot's errata command?
Here is the output for the errata command:
> => errata
> Work-around for Erratum CPU-A003999 enabled
> Work-around for Erratum DDR-A003473 enabled
> Work-around for Erratum ESDHC111 enabled
> Work-around for Erratum DDR-A003 enabled
> Work-around for Erratum A004510 enabled
> Work-around for Erratum SRIO-A004034 enabled
> Work-around for Erratum A004849 is not enabled
> Work-around for Erratum A004580 is not enabled
> Work-around for Erratum USB14 enabled
>
> Especially if the workarounds for A-004580 and A-004849 are in place.
>
So both are not enabled, I am going to fix that. Surprisingly, A-004580 is not
defined for the P2041 in u-boot even though it is also present in the P2041's
errata sheet, I had to enable it myself.
However, I expect that enabling the workarounds for these 2 Errata are good for
the system but it will not solve the PCIe EDAC problem.
Thank you for the input.
Valentin
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-03-20 10:44 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-03-19 12:46 EDAC PCIe errors when scannning the bus Valentin Longchamp
2014-03-19 15:54 ` Johannes Thumshirn
2014-03-19 15:54 ` Johannes Thumshirn
2014-03-20 10:44 ` Valentin Longchamp
2014-03-20 10:44 ` Valentin Longchamp
2014-03-19 19:58 ` Rajat Jain
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