[Xenomai] IRQ Handler latency

[Xenomai] IRQ Handler latency

[Newell Jensen]

Hello,

I have successfully created an RTDM driver that uses the EPIT timer on the
i.mx6dl-sabresd board.  The reason I created this driver is I wanted to see
what the hard interrupt latency is using Xenomai.

AFAIK, I am using the RTDM skin in the proper way.  However, I wanted to
run my code by the experts (you guys), to see if there is any improvements
that I can make.

Here is a link to my code:  http://pastebin.com/TFWLq9mq

My questions are:

1. Is there anything that I am not doing in my code that I should be to
reduce interrupt latency?

2. Is there a way to set the priority for a kernel module like the one I
have?

3. Is there an easy way to see the priorities of all irqs both in Xenomai
and Linux?

Essentially we want to get a core as isolated as possible so that only our
one time critical interrupt handler is running on that at the highest
priority.

Thanks,

Newell

Re: [Xenomai] IRQ Handler latency

[Gilles Chanteperdrix]

Le 29/03/2014 00:41, Newell Jensen a écrit :
> Hello,
> 
> I have successfully created an RTDM driver that uses the EPIT timer on the
> i.mx6dl-sabresd board.  The reason I created this driver is I wanted to see
> what the hard interrupt latency is using Xenomai.
> 
> AFAIK, I am using the RTDM skin in the proper way.  However, I wanted to
> run my code by the experts (you guys), to see if there is any improvements
> that I can make.
> 
> Here is a link to my code:  http://pastebin.com/TFWLq9mq
> 
> My questions are:
> 
> 1. Is there anything that I am not doing in my code that I should be to
> reduce interrupt latency?

You can remove some useless stuff from the interrupt handler: testing
rtdm_in_rt_context is useless, calling rtdm_lock_get_irqsave is useless,
as irqs are already off.

> 
> 2. Is there a way to set the priority for a kernel module like the one I
> have?

It does not make sense to talk about the priority of a kernel module.

> 
> 3. Is there an easy way to see the priorities of all irqs both in Xenomai
> and Linux?

Xenomai irqs are not threaded, so there is no such thing as an irq priority.

But why do you ask all this, have you compared the latencies you measure
with those of the "latency" test, are they not comparable?
Do you have the patch which disables write-allocate in the imx6 L2 cache?


-- 
Gilles.

Re: [Xenomai] IRQ Handler latency

[Gilles Chanteperdrix]

Le 29/03/2014 00:41, Newell Jensen a écrit :
> Hello,
> 
> I have successfully created an RTDM driver that uses the EPIT timer on the
> i.mx6dl-sabresd board.  The reason I created this driver is I wanted to see
> what the hard interrupt latency is using Xenomai.
> 
> AFAIK, I am using the RTDM skin in the proper way.  However, I wanted to
> run my code by the experts (you guys), to see if there is any improvements
> that I can make.
> 
> Here is a link to my code:  http://pastebin.com/TFWLq9mq
> 
> My questions are:
> 
> 1. Is there anything that I am not doing in my code that I should be to
> reduce interrupt latency?

Also, there is probably not much to gain by using this EPIT compared to
using Xenomai timer system. Xenomai timers are just that: executed on a
counter interruption, except that Xenomai timers have an anticipation
system which will help improving the perceived latency.


-- 
Gilles.

Re: [Xenomai] IRQ Handler latency

[Gilles Chanteperdrix]

Le 29/03/2014 00:41, Newell Jensen a écrit :
> Hello,
> 
> I have successfully created an RTDM driver that uses the EPIT timer on the
> i.mx6dl-sabresd board.  The reason I created this driver is I wanted to see
> what the hard interrupt latency is using Xenomai.
> 
> AFAIK, I am using the RTDM skin in the proper way.  However, I wanted to
> run my code by the experts (you guys), to see if there is any improvements
> that I can make.
> 
> Here is a link to my code:  http://pastebin.com/TFWLq9mq

Also, the code measuring latency seems all wrong. Debugging this looks
like a waste of time:
- we provide the latency test, which we hope is reasonably debugged, so
duplicating the effort is a waste of (our) time;
- from the code, I would guess the EPIT runs at 6 MHz, whereas the
cortex A9 has timers running at 400 or 500 MHz, which results in lower
latencies for accessing their registers.

-- 
Gilles.