Re: 15-rc1: radeon modesetting fails

["Christian König" <deathsimple@vodafone.de>]

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Hi Borislav,

thanks for the logs, those were indeed quite helpful.

Attached are two patches, the first one tries to solve the problem by 
increasing the accuracy of the parameters if we don't match exactly and 
the second improves the logging of the calculation process by dumping a 
bunch of intermediate values used.

Please apply both on top of my drm-fixes-3.15-wip branch you are already 
using, if the first one doesn't solve the problem then please provide 
new dmesg logs with drm.debug=0xE.

Thanks in advance,
Christian.

Am 15.04.2014 16:24, schrieb Borislav Petkov:
> On Tue, Apr 15, 2014 at 03:09:02PM +0200, Christian König wrote:
>>> Does reverting:
>>> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=32167016076f714f0e35e287fbead7de0f1fb179
>>> fix the issue?  We may need to tweak the pll parameters for older asics.
>> Yeah, indeed the most likely cause. Please provide dmesg outputs created
>> with drm.ebug=0xe for the old and the new kernel.
> Hey, I finally haz 15-rc1+ running here. And I can even see something!
>
> :-)
>
> Ok, so I reverted 32167016076f ontop of Christian's drm-fixes-3.15-wip
> branch which didn't apply cleanly. So I ended up fixing the conflicts
> and got the revert below.
>
> With it, the machine booted fine, so it looks like the revert worked.
>
> Christian, I'm sending dmesg outputs in another private mail to you
> guys.
>
> Thanks.

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>From 19de393134c00989b5b1cc5e6dd4ed444a897ace Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Wed, 16 Apr 2014 11:54:21 +0200
Subject: [PATCH 1/2] drm/radeon: improve PLL params if we don't match exactly
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Otherwise we might be quite off on older chipsets.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/radeon/radeon_display.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 2f42912..fb3b505 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 	unsigned post_div_min, post_div_max, post_div;
 	unsigned ref_div_min, ref_div_max, ref_div;
 	unsigned post_div_best, diff_best;
-	unsigned nom, den, tmp;
+	unsigned nom, den;
 
 	/* determine allowed feedback divider range */
 	fb_div_min = pll->min_feedback_div;
@@ -941,22 +941,23 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 	ref_div_max = min(210 / post_div, ref_div_max);
 
 	/* get matching reference and feedback divider */
-	ref_div = max(den / post_div, 1u);
-	fb_div = nom;
+	ref_div = DIV_ROUND_CLOSEST(den, post_div);
+	fb_div = DIV_ROUND_CLOSEST(nom * ref_div * post_div, den);
 
 	/* we're almost done, but reference and feedback
 	   divider might be to large now */
 
-	tmp = ref_div;
+	nom = fb_div;
+	den = ref_div;
 
         if (fb_div > fb_div_max) {
-		ref_div = ref_div * fb_div_max / fb_div;
+		ref_div = DIV_ROUND_CLOSEST(den * fb_div_max, nom);
 		fb_div = fb_div_max;
 	}
 
 	if (ref_div > ref_div_max) {
 		ref_div = ref_div_max;
-		fb_div = nom * ref_div_max / tmp;
+		fb_div = DIV_ROUND_CLOSEST(nom * ref_div_max, den);
 	}
 
 	/* reduce the numbers to a simpler ratio once more */
-- 
1.9.1


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>From e0e6fa5c0b7df9a3de1784082a878bcfebb8a941 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Wed, 16 Apr 2014 11:57:28 +0200
Subject: [PATCH 2/2] drm/radeon: improve logging of PLL parameter calculation
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/radeon/radeon_display.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index fb3b505..037db45 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -820,6 +820,9 @@ static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 {
 	unsigned tmp;
 
+	DRM_DEBUG_KMS("nom: %d den: %d nom_min %d den_min %d\n",
+		      *nom, *den, nom_min, den_min);
+
 	/* reduce the numbers to a simpler ratio */
 	tmp = gcd(*nom, *den);
 	*nom /= tmp;
@@ -876,6 +879,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 		fb_div_max *= 10;
 	}
 
+	DRM_DEBUG_KMS("fb_div_min: %d fb_div_max: %d\n",
+		      fb_div_min, fb_div_max);
+
 	/* determine allowed ref divider range */
 	if (pll->flags & RADEON_PLL_USE_REF_DIV)
 		ref_div_min = pll->reference_div;
@@ -883,6 +889,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 		ref_div_min = pll->min_ref_div;
 	ref_div_max = pll->max_ref_div;
 
+	DRM_DEBUG_KMS("ref_div_min: %d ref_div_max: %d\n",
+		      ref_div_min, ref_div_max);
+
 	/* determine allowed post divider range */
 	if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 		post_div_min = pll->post_div;
@@ -912,6 +921,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 			post_div_max = pll->max_post_div;
 	}
 
+	DRM_DEBUG_KMS("post_div_min: %d post_div_max: %d\n",
+		      post_div_min, post_div_max);
+
 	/* represent the searched ratio as fractional number */
 	nom = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10;
 	den = pll->reference_freq;
@@ -980,7 +992,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
 	*post_div_p = post_div;
 
 	DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
-		      freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p,
+		      freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
 		      ref_div, post_div);
 }
 
-- 
1.9.1


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