Re: [PATCH v3 4/7] ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate

[Tero Kristo <t-kristo@ti.com>]

On 05/05/2014 12:54 PM, Roger Quadros wrote:
> This clock gate description is missing in the older Reference manuals.
> It is present on the SoC to provide 960MHz reference clock to the
> internal USB PHYs.
>
> Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900,
> Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL
>
> Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and
> usb_otg_ss2_refclk960m.
>
> CC: Benoît Cousson <bcousson@baylibre.com>
> CC: Tero Kristo <t-kristo@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Got myself to download the latest copy of the TRM, so this patch looks 
valid.

Acked-by: Tero Kristo <t-kristo@ti.com>

> ---
>   arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++++++++++--
>   1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index cfb8fc7..c767687 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -1386,6 +1386,14 @@
>   		ti,dividers = <1>, <8>;
>   	};
>
> +	l3init_960m_gfclk: l3init_960m_gfclk {
> +		#clock-cells = <0>;
> +		compatible = "ti,gate-clock";
> +		clocks = <&dpll_usb_clkdcoldo>;
> +		ti,bit-shift = <8>;
> +		reg = <0x06c0>;
> +	};
> +
>   	dss_32khz_clk: dss_32khz_clk {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> @@ -1533,7 +1541,7 @@
>   	usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> -		clocks = <&dpll_usb_clkdcoldo>;
> +		clocks = <&l3init_960m_gfclk>;
>   		ti,bit-shift = <8>;
>   		reg = <0x13f0>;
>   	};
> @@ -1541,7 +1549,7 @@
>   	usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
>   		#clock-cells = <0>;
>   		compatible = "ti,gate-clock";
> -		clocks = <&dpll_usb_clkdcoldo>;
> +		clocks = <&l3init_960m_gfclk>;
>   		ti,bit-shift = <8>;
>   		reg = <0x1340>;
>   	};
>

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