Re: Support of Micron SPI flash (size > 16MB)

Re: Support of Micron SPI flash (size > 16MB)

[Mark Brown]

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On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu@freescale.com wrote:

> 2.       What are the changes needed for SPI controller to support 4 byte addressing?

If the SPI controller is a genuine SPI controller and not something
specially optimised for flash it shouldn't need any changes, it doesn't
know anything about the data it's sending.  The SPI flash code might
need updating though, I don't know about that.

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Re: Support of Micron SPI flash (size > 16MB)

[Mark Brown]

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On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org wrote:

> 2.       What are the changes needed for SPI controller to support 4 byte addressing?

If the SPI controller is a genuine SPI controller and not something
specially optimised for flash it shouldn't need any changes, it doesn't
know anything about the data it's sending.  The SPI flash code might
need updating though, I don't know about that.

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Re: Support of Micron SPI flash (size > 16MB)

[Brian Norris]

On Fri, May 09, 2014 at 11:44:04AM +0100, Mark Brown wrote:
> On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu@freescale.com wrote:
> > 2.       What are the changes needed for SPI controller to support 4 byte addressing?
> 
> If the SPI controller is a genuine SPI controller and not something
> specially optimised for flash it shouldn't need any changes, it doesn't
> know anything about the data it's sending.

Right. A true SPI controller doesn't need to know anything about
addressing modes.

> The SPI flash code might
> need updating though, I don't know about that.

The SPI flash code in MTD (m25p80.c, some of which is moving to
drivers/mtd/spi-nor/ in -next) already supports 4-byte addressing for
most flash. Check for flash support there.

You might also look at my comments in this commit, regarding the
different types of "4-byte addressing":

commit 87c9511fba2bd069a35e1312587a29e112fc0cd6
Author: Brian Norris <computersforpeace@gmail.com>
Date:   Thu Apr 11 01:34:57 2013 -0700

    mtd: m25p80: utilize dedicated 4-byte addressing commands

But again, most of this should just work(TM) for true SPI controllers.

Regards,
Brian

Re: Support of Micron SPI flash (size > 16MB)

[Brian Norris]

On Fri, May 09, 2014 at 11:44:04AM +0100, Mark Brown wrote:
> On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org wrote:
> > 2.       What are the changes needed for SPI controller to support 4 byte addressing?
> 
> If the SPI controller is a genuine SPI controller and not something
> specially optimised for flash it shouldn't need any changes, it doesn't
> know anything about the data it's sending.

Right. A true SPI controller doesn't need to know anything about
addressing modes.

> The SPI flash code might
> need updating though, I don't know about that.

The SPI flash code in MTD (m25p80.c, some of which is moving to
drivers/mtd/spi-nor/ in -next) already supports 4-byte addressing for
most flash. Check for flash support there.

You might also look at my comments in this commit, regarding the
different types of "4-byte addressing":

commit 87c9511fba2bd069a35e1312587a29e112fc0cd6
Author: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Date:   Thu Apr 11 01:34:57 2013 -0700

    mtd: m25p80: utilize dedicated 4-byte addressing commands

But again, most of this should just work(TM) for true SPI controllers.

Regards,
Brian
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RE: Support of Micron SPI flash (size > 16MB)

[Mingkai.Hu]

> -----Original Message-----
> From: Brian Norris [mailto:computersforpeace@gmail.com]
> Sent: Friday, May 16, 2014 2:19 PM
> To: Mark Brown
> Cc: Hu Mingkai-B21284; dwmw2@infradead.org;
> vivien.didelot@savoirfairelinux.com; linux-mtd@lists.infradead.org;
> linux-spi@vger.kernel.org
> Subject: Re: Support of Micron SPI flash (size > 16MB)
> 
> On Fri, May 09, 2014 at 11:44:04AM +0100, Mark Brown wrote:
> > On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu@freescale.com
> wrote:
> > > 2.       What are the changes needed for SPI controller to support 4
> byte addressing?
> >
> > If the SPI controller is a genuine SPI controller and not something
> > specially optimised for flash it shouldn't need any changes, it
> > doesn't know anything about the data it's sending.
> 
> Right. A true SPI controller doesn't need to know anything about
> addressing modes.
> 
> > The SPI flash code might
> > need updating though, I don't know about that.
> 
> The SPI flash code in MTD (m25p80.c, some of which is moving to
> drivers/mtd/spi-nor/ in -next) already supports 4-byte addressing for
> most flash. Check for flash support there.
> 
> You might also look at my comments in this commit, regarding the
> different types of "4-byte addressing":
> 
> commit 87c9511fba2bd069a35e1312587a29e112fc0cd6
> Author: Brian Norris <computersforpeace@gmail.com>
> Date:   Thu Apr 11 01:34:57 2013 -0700
> 
>     mtd: m25p80: utilize dedicated 4-byte addressing commands
> 
> But again, most of this should just work(TM) for true SPI controllers.
> 

Thanks for your info, Brian. We are using N25Q512A Micron SPI flash. Micron implemented
two commands to enter and exit 4 bytes address mode.

Another question is for erase and program command. From the datasheet, not only the WTITE
ENABLE command need to be issued before the command can be executed, but also a special
READ FLAG STATUS RESISTER command need to be issued after the erase/program command which
is not implemented in the upstream code. We implement the READ flag operation and erase
can work, but write still fail.

I saw somebody has added the Micron larger SPI flash (>16Mb) support, so I'd like to know
if they run into such issue.

Thanks,
Mingkai

RE: Support of Micron SPI flash (size > 16MB)

[Mingkai.Hu-KZfg59tc24xl57MIdRCFDg]

> -----Original Message-----
> From: Brian Norris [mailto:computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org]
> Sent: Friday, May 16, 2014 2:19 PM
> To: Mark Brown
> Cc: Hu Mingkai-B21284; dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org;
> vivien.didelot-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org; linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Subject: Re: Support of Micron SPI flash (size > 16MB)
> 
> On Fri, May 09, 2014 at 11:44:04AM +0100, Mark Brown wrote:
> > On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org
> wrote:
> > > 2.       What are the changes needed for SPI controller to support 4
> byte addressing?
> >
> > If the SPI controller is a genuine SPI controller and not something
> > specially optimised for flash it shouldn't need any changes, it
> > doesn't know anything about the data it's sending.
> 
> Right. A true SPI controller doesn't need to know anything about
> addressing modes.
> 
> > The SPI flash code might
> > need updating though, I don't know about that.
> 
> The SPI flash code in MTD (m25p80.c, some of which is moving to
> drivers/mtd/spi-nor/ in -next) already supports 4-byte addressing for
> most flash. Check for flash support there.
> 
> You might also look at my comments in this commit, regarding the
> different types of "4-byte addressing":
> 
> commit 87c9511fba2bd069a35e1312587a29e112fc0cd6
> Author: Brian Norris <computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Date:   Thu Apr 11 01:34:57 2013 -0700
> 
>     mtd: m25p80: utilize dedicated 4-byte addressing commands
> 
> But again, most of this should just work(TM) for true SPI controllers.
> 

Thanks for your info, Brian. We are using N25Q512A Micron SPI flash. Micron implemented
two commands to enter and exit 4 bytes address mode.

Another question is for erase and program command. From the datasheet, not only the WTITE
ENABLE command need to be issued before the command can be executed, but also a special
READ FLAG STATUS RESISTER command need to be issued after the erase/program command which
is not implemented in the upstream code. We implement the READ flag operation and erase
can work, but write still fail.

I saw somebody has added the Micron larger SPI flash (>16Mb) support, so I'd like to know
if they run into such issue.

Thanks,
Mingkai
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Re: Support of Micron SPI flash (size > 16MB)

[Huang Shijie]

于 2014年05月16日 16:15, Mingkai.Hu@freescale.com 写道:
> Another question is for erase and program command. From the datasheet, not only the WTITE
> ENABLE command need to be issued before the command can be executed, but also a special
> READ FLAG STATUS RESISTER command need to be issued after the erase/program command which
> is not implemented in the upstream code. We implement the READ flag operation and erase
> can work, but write still fail.
>
> I saw somebody has added the Micron larger SPI flash (>16Mb) support, so I'd like to know
> if they run into such issue.
Yes, we have noticed this issue:

Please see this patch:
http://lists.infradead.org/pipermail/linux-mtd/2014-April/053571.html

thanks
Huang Shijie

Re: Support of Micron SPI flash (size > 16MB)

[Huang Shijie]

于 2014年05月16日 16:15, Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org 写道:
> Another question is for erase and program command. From the datasheet, not only the WTITE
> ENABLE command need to be issued before the command can be executed, but also a special
> READ FLAG STATUS RESISTER command need to be issued after the erase/program command which
> is not implemented in the upstream code. We implement the READ flag operation and erase
> can work, but write still fail.
>
> I saw somebody has added the Micron larger SPI flash (>16Mb) support, so I'd like to know
> if they run into such issue.
Yes, we have noticed this issue:

Please see this patch:
http://lists.infradead.org/pipermail/linux-mtd/2014-April/053571.html

thanks
Huang Shijie
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RE: Support of Micron SPI flash (size > 16MB)

[Mingkai.Hu]

> -----Original Message-----
> From: Huang Shijie [mailto:b32955@freescale.com]
> Sent: Friday, May 16, 2014 4:33 PM
> To: Hu Mingkai-B21284
> Cc: Brian Norris; Mark Brown; linux-mtd@lists.infradead.org; linux-
> spi@vger.kernel.org; dwmw2@infradead.org;
> vivien.didelot@savoirfairelinux.com
> Subject: Re: Support of Micron SPI flash (size > 16MB)
> 
> 于 2014年05月16日 16:15, Mingkai.Hu@freescale.com 写道:
> > Another question is for erase and program command. From the datasheet,
> > not only the WTITE ENABLE command need to be issued before the command
> > can be executed, but also a special READ FLAG STATUS RESISTER command
> > need to be issued after the erase/program command which is not
> > implemented in the upstream code. We implement the READ flag operation
> and erase can work, but write still fail.
> >
> > I saw somebody has added the Micron larger SPI flash (>16Mb) support,
> > so I'd like to know if they run into such issue.
> Yes, we have noticed this issue:
> 
> Please see this patch:
> http://lists.infradead.org/pipermail/linux-mtd/2014-April/053571.html
> 
Thanks for your info, Shijie. We implemented this in a similar way.

Thanks,
Mingkai

RE: Support of Micron SPI flash (size > 16MB)

[Mingkai.Hu-KZfg59tc24xl57MIdRCFDg]

> -----Original Message-----
> From: Huang Shijie [mailto:b32955@freescale.com]
> Sent: Friday, May 16, 2014 4:33 PM
> To: Hu Mingkai-B21284
> Cc: Brian Norris; Mark Brown; linux-mtd@lists.infradead.org; linux-
> spi@vger.kernel.org; dwmw2@infradead.org;
> vivien.didelot@savoirfairelinux.com
> Subject: Re: Support of Micron SPI flash (size > 16MB)
> 
> 于 2014年05月16日 16:15, Mingkai.Hu@freescale.com 写道:
> > Another question is for erase and program command. From the datasheet,
> > not only the WTITE ENABLE command need to be issued before the command
> > can be executed, but also a special READ FLAG STATUS RESISTER command
> > need to be issued after the erase/program command which is not
> > implemented in the upstream code. We implement the READ flag operation
> and erase can work, but write still fail.
> >
> > I saw somebody has added the Micron larger SPI flash (>16Mb) support,
> > so I'd like to know if they run into such issue.
> Yes, we have noticed this issue:
> 
> Please see this patch:
> http://lists.infradead.org/pipermail/linux-mtd/2014-April/053571.html
> 
Thanks for your info, Shijie. We implemented this in a similar way.

Thanks,
Mingkai

RE: Support of Micron SPI flash (size > 16MB)

[Mingkai.Hu]

> -----Original Message-----
> From: Mark Brown [mailto:broonie@kernel.org]
> Sent: Friday, May 09, 2014 6:44 PM
> To: Hu Mingkai-B21284
> Cc: linux-spi@vger.kernel.org; linux-mtd@lists.infradead.org;
> dwmw2@infradead.org; vivien.didelot@savoirfairelinux.com
> Subject: Re: Support of Micron SPI flash (size > 16MB)
> 
> On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu@freescale.com wrote:
> 
> > 2.       What are the changes needed for SPI controller to support 4
> byte addressing?
> 
> If the SPI controller is a genuine SPI controller and not something
> specially optimised for flash it shouldn't need any changes, it doesn't
> know anything about the data it's sending.  The SPI flash code might need
> updating though, I don't know about that.

Thanks for your info.
Mingkai

RE: Support of Micron SPI flash (size > 16MB)

[Mingkai.Hu-KZfg59tc24xl57MIdRCFDg]

> -----Original Message-----
> From: Mark Brown [mailto:broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org]
> Sent: Friday, May 09, 2014 6:44 PM
> To: Hu Mingkai-B21284
> Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org; vivien.didelot-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/@public.gmane.org
> Subject: Re: Support of Micron SPI flash (size > 16MB)
> 
> On Fri, May 09, 2014 at 10:25:04AM +0000, Mingkai.Hu-KZfg59tc24xl57MIdRCFDg@public.gmane.org wrote:
> 
> > 2.       What are the changes needed for SPI controller to support 4
> byte addressing?
> 
> If the SPI controller is a genuine SPI controller and not something
> specially optimised for flash it shouldn't need any changes, it doesn't
> know anything about the data it's sending.  The SPI flash code might need
> updating though, I don't know about that.

Thanks for your info.
Mingkai
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