From: Emil Velikov <emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Ilia Mirkin <imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>,
mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: "10.2"
<mesa-stable-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>,
emil.l.velikov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Subject: Re: [Mesa-dev] [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil
Date: Wed, 21 May 2014 19:57:14 +0100 [thread overview]
Message-ID: <537CF70A.4000905@gmail.com> (raw)
In-Reply-To: <1400629206-4447-3-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
On 21/05/14 00:39, Ilia Mirkin wrote:
> From: Christoph Bumiller <e0425955-oe7qfRrRQffzPE21tAIdciO7C/xPubJB@public.gmane.org>
>
> [imirkin: add logic to also clear the "regular" scissors]
Can you please share why are you've added the "regular" scissors ?
Does it matter if we set the screen scissors before the render target params?
Thanks
Emil
> Reviewed-by: Ilia Mirkin <imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
> Cc: "10.2" <mesa-stable-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> ---
> src/gallium/drivers/nouveau/nv50/nv50_surface.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> index 1f37527..6e68fb8 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
> @@ -288,6 +288,14 @@ nv50_clear_render_target(struct pipe_context *pipe,
>
> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>
> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
> + PUSH_DATA (push, ( width << 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);
> + nv50->scissors_dirty |= 1;
> +
> BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1);
> PUSH_DATA (push, 1);
> BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5);
> @@ -325,7 +333,7 @@ nv50_clear_render_target(struct pipe_context *pipe,
> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
> }
>
> - nv50->dirty |= NV50_NEW_FRAMEBUFFER;
> + nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
> }
>
> static void
> @@ -364,6 +372,14 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
>
> PUSH_REFN(push, bo, mt->base.domain | NOUVEAU_BO_WR);
>
> + BEGIN_NV04(push, NV50_3D(SCREEN_SCISSOR_HORIZ), 2);
> + PUSH_DATA (push, ( width << 16) | dstx);
> + PUSH_DATA (push, (height << 16) | dsty);
> + BEGIN_NV04(push, NV50_3D(SCISSOR_HORIZ(0)), 2);
> + PUSH_DATA (push, 8192 << 16);
> + PUSH_DATA (push, 8192 << 16);
> + nv50->scissors_dirty |= 1;
> +
> BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
> PUSH_DATAh(push, bo->offset + sf->offset);
> PUSH_DATA (push, bo->offset + sf->offset);
> @@ -390,7 +406,7 @@ nv50_clear_depth_stencil(struct pipe_context *pipe,
> (z << NV50_3D_CLEAR_BUFFERS_LAYER__SHIFT));
> }
>
> - nv50->dirty |= NV50_NEW_FRAMEBUFFER;
> + nv50->dirty |= NV50_NEW_FRAMEBUFFER | NV50_NEW_SCISSOR;
> }
>
> void
>
next prev parent reply other threads:[~2014-05-21 18:57 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-20 23:39 [PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine Ilia Mirkin
2014-05-20 23:39 ` [PATCH 02/12] nv50: setup scissors on clear_render_target/depth_stencil Ilia Mirkin
[not found] ` <1400629206-4447-3-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2014-05-21 18:57 ` Emil Velikov [this message]
[not found] ` <537CF70A.4000905-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-05-21 18:59 ` [Mesa-dev] " Ilia Mirkin
2014-05-21 19:06 ` Emil Velikov
2014-05-20 23:39 ` [PATCH 03/12] nv50, nvc0: set constbufs dirty on pipe context switch Ilia Mirkin
2014-05-20 23:39 ` [PATCH 05/12] nv50/ir/opt: fix constant folding with saturate modifier Ilia Mirkin
2014-05-20 23:40 ` [PATCH 07/12] nv50/ir/tgsi: optimize KIL Ilia Mirkin
[not found] ` <1400629206-4447-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2014-05-20 23:39 ` [PATCH 01/12] nv50, nvc0: always pull out bufctx on context destruction Ilia Mirkin
2014-05-20 23:39 ` [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result Ilia Mirkin
2014-05-21 18:51 ` Emil Velikov
[not found] ` <537CF597.4080406-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-05-21 18:53 ` [Mesa-dev] " Ilia Mirkin
[not found] ` <CAKb7Uvj1EomVeAwqFdguuP9xQ1dDkRGDVc9N7239b8O+aL-VrQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-05-21 19:01 ` Emil Velikov
[not found] ` <537CF7F7.1010504-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-05-21 19:03 ` Ilia Mirkin
[not found] ` <CAKb7UvgQ3Pz8CUFTGi16x+Ay=0PezJrOuw0kWXLf-rnDeLCgDw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-05-21 19:04 ` Ilia Mirkin
2014-05-20 23:40 ` [PATCH 06/12] nv50/ir: fix lowering of predicated instructions (without defs) Ilia Mirkin
2014-05-20 23:40 ` [PATCH 08/12] nv50,nvc0: handle guard band defines Ilia Mirkin
2014-05-20 23:40 ` [PATCH 09/12] nv50, nvc0: allow 15, 16, 30 bpp display formats Ilia Mirkin
2014-05-20 23:40 ` [PATCH 10/12] nvc0: use PRIxPTR for sizeof() Ilia Mirkin
2014-05-20 23:40 ` [PATCH 11/12] nvc0: assert that we have vertex elements state Ilia Mirkin
2014-05-20 23:40 ` [PATCH 12/12] nv50: count wrapped textures towards the tex_obj count Ilia Mirkin
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