* [PATCH 0/2] nvc0: support for GK20A (Tegra K1)
@ 2014-05-27 4:59 Alexandre Courbot
[not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-27 7:03 ` [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A Alexandre Courbot
0 siblings, 2 replies; 12+ messages in thread
From: Alexandre Courbot @ 2014-05-27 4:59 UTC (permalink / raw)
To: Ilia Mirkin; +Cc: linux-tegra, nouveau, gnurou, mesa-dev
The following 2 patches make it possible to run Mesa programs on GK20A
(Tegra K1).
GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class
as well as the same ISA as GK110 (SM35). Taking these differences into account
is sufficient to successfully render simple off-screen buffers.
Alexandre Courbot (2):
nvc0: add GK20A 3D class
nvc0: use SM35 ISA with GK20A
src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 +
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +-
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++----
src/gallium/drivers/nouveau/nv_object.xml.h | 1 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++-
5 files changed, 20 insertions(+), 6 deletions(-)
--
1.9.3
^ permalink raw reply [flat|nested] 12+ messages in thread[parent not found: <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* [PATCH 1/2] nvc0: add GK20A 3D class [not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-05-27 4:59 ` Alexandre Courbot [not found] ` <1401166783-24086-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-05-27 4:59 ` [PATCH 2/2] nvc0: use SM35 ISA with GK20A Alexandre Courbot ` (2 subsequent siblings) 3 siblings, 1 reply; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 4:59 UTC (permalink / raw) To: Ilia Mirkin Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected. Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h index 4c93e6564838..0a0e187dc028 100644 --- a/src/gallium/drivers/nouveau/nv_object.xml.h +++ b/src/gallium/drivers/nouveau/nv_object.xml.h @@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC8_3D_CLASS 0x00009297 #define NVE4_3D_CLASS 0x0000a097 #define NVF0_3D_CLASS 0x0000a197 +#define NVEA_3D_CLASS 0x0000a297 #define GM107_3D_CLASS 0x0000b097 #define NV50_2D_CLASS 0x0000502d #define NVC0_2D_CLASS 0x0000902d diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index cccfe2bba23d..95e5ef81cd79 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class = NVF0_3D_CLASS; break; case 0xe0: - obj_class = NVE4_3D_CLASS; + switch (dev->chipset) { + case 0xea: + obj_class = NVEA_3D_CLASS; + break; + default: + obj_class = NVE4_3D_CLASS; + break; + } break; case 0xd0: obj_class = NVC8_3D_CLASS; -- 1.9.3 ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <1401166783-24086-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 1/2] nvc0: add GK20A 3D class [not found] ` <1401166783-24086-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-05-27 5:29 ` Ilia Mirkin [not found] ` <CAKb7Uvjvo=9u-mSH01AHidOBS_6cE88kpy+H=QoJQprtLekvKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 12+ messages in thread From: Ilia Mirkin @ 2014-05-27 5:29 UTC (permalink / raw) To: Alexandre Courbot Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Alexandre Courbot On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > GK20A is mostly compatible with GK104, but features a new 3D > class. Add it to the relevant header and use it when GK20A is > detected. > > Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > src/gallium/drivers/nouveau/nv_object.xml.h | 1 + > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h > index 4c93e6564838..0a0e187dc028 100644 > --- a/src/gallium/drivers/nouveau/nv_object.xml.h > +++ b/src/gallium/drivers/nouveau/nv_object.xml.h > @@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > #define NVC8_3D_CLASS 0x00009297 > #define NVE4_3D_CLASS 0x0000a097 > #define NVF0_3D_CLASS 0x0000a197 > +#define NVEA_3D_CLASS 0x0000a297 > #define GM107_3D_CLASS 0x0000b097 > #define NV50_2D_CLASS 0x0000502d > #define NVC0_2D_CLASS 0x0000902d > diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > index cccfe2bba23d..95e5ef81cd79 100644 > --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c > @@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) > obj_class = NVF0_3D_CLASS; > break; > case 0xe0: > - obj_class = NVE4_3D_CLASS; > + switch (dev->chipset) { > + case 0xea: > + obj_class = NVEA_3D_CLASS; Again, would be nice to be consistent with the way you set the ISA... perhaps change this to a >= as well? But I guess the two could be disconnected. Up to you, just thought I'd bring it up. > + break; > + default: > + obj_class = NVE4_3D_CLASS; > + break; > + } > break; > case 0xd0: > obj_class = NVC8_3D_CLASS; > -- > 1.9.3 > ^ permalink raw reply [flat|nested] 12+ messages in thread
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* Re: [PATCH 1/2] nvc0: add GK20A 3D class [not found] ` <CAKb7Uvjvo=9u-mSH01AHidOBS_6cE88kpy+H=QoJQprtLekvKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-05-27 6:35 ` Alexandre Courbot [not found] ` <53843236.4030508-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 0 siblings, 1 reply; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 6:35 UTC (permalink / raw) To: Ilia Mirkin Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org On 05/27/2014 02:29 PM, Ilia Mirkin wrote: > On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: >> GK20A is mostly compatible with GK104, but features a new 3D >> class. Add it to the relevant header and use it when GK20A is >> detected. >> >> Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> --- >> src/gallium/drivers/nouveau/nv_object.xml.h | 1 + >> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- >> 2 files changed, 9 insertions(+), 1 deletion(-) >> >> diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h >> index 4c93e6564838..0a0e187dc028 100644 >> --- a/src/gallium/drivers/nouveau/nv_object.xml.h >> +++ b/src/gallium/drivers/nouveau/nv_object.xml.h >> @@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. >> #define NVC8_3D_CLASS 0x00009297 >> #define NVE4_3D_CLASS 0x0000a097 >> #define NVF0_3D_CLASS 0x0000a197 >> +#define NVEA_3D_CLASS 0x0000a297 >> #define GM107_3D_CLASS 0x0000b097 >> #define NV50_2D_CLASS 0x0000502d >> #define NVC0_2D_CLASS 0x0000902d >> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >> index cccfe2bba23d..95e5ef81cd79 100644 >> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >> @@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) >> obj_class = NVF0_3D_CLASS; >> break; >> case 0xe0: >> - obj_class = NVE4_3D_CLASS; >> + switch (dev->chipset) { >> + case 0xea: >> + obj_class = NVEA_3D_CLASS; > > Again, would be nice to be consistent with the way you set the ISA... > perhaps change this to a >= as well? But I guess the two could be > disconnected. Up to you, just thought I'd bring it up. Right below we have the following being done: switch (dev->chipset) { case 0xc8: obj_class = NVC8_3D_CLASS; break; case 0xc1: obj_class = NVC1_3D_CLASS; break; default: obj_class = NVC0_3D_CLASS; break; } Shouldn't we try to be consistent with this more local example instead? ^ permalink raw reply [flat|nested] 12+ messages in thread
[parent not found: <53843236.4030508-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 1/2] nvc0: add GK20A 3D class [not found] ` <53843236.4030508-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-05-27 15:48 ` Ilia Mirkin 0 siblings, 0 replies; 12+ messages in thread From: Ilia Mirkin @ 2014-05-27 15:48 UTC (permalink / raw) To: Alexandre Courbot Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Alexandre Courbot On Tue, May 27, 2014 at 2:35 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > On 05/27/2014 02:29 PM, Ilia Mirkin wrote: >> >> On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> wrote: >>> >>> GK20A is mostly compatible with GK104, but features a new 3D >>> class. Add it to the relevant header and use it when GK20A is >>> detected. >>> >>> Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >>> --- >>> src/gallium/drivers/nouveau/nv_object.xml.h | 1 + >>> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- >>> 2 files changed, 9 insertions(+), 1 deletion(-) >>> >>> diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h >>> b/src/gallium/drivers/nouveau/nv_object.xml.h >>> index 4c93e6564838..0a0e187dc028 100644 >>> --- a/src/gallium/drivers/nouveau/nv_object.xml.h >>> +++ b/src/gallium/drivers/nouveau/nv_object.xml.h >>> @@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE >>> SOFTWARE. >>> #define NVC8_3D_CLASS >>> 0x00009297 >>> #define NVE4_3D_CLASS >>> 0x0000a097 >>> #define NVF0_3D_CLASS >>> 0x0000a197 >>> +#define NVEA_3D_CLASS >>> 0x0000a297 >>> #define GM107_3D_CLASS >>> 0x0000b097 >>> #define NV50_2D_CLASS >>> 0x0000502d >>> #define NVC0_2D_CLASS >>> 0x0000902d >>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >>> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >>> index cccfe2bba23d..95e5ef81cd79 100644 >>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c >>> @@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) >>> obj_class = NVF0_3D_CLASS; >>> break; >>> case 0xe0: >>> - obj_class = NVE4_3D_CLASS; >>> + switch (dev->chipset) { >>> + case 0xea: >>> + obj_class = NVEA_3D_CLASS; >> >> >> Again, would be nice to be consistent with the way you set the ISA... >> perhaps change this to a >= as well? But I guess the two could be >> disconnected. Up to you, just thought I'd bring it up. > > > Right below we have the following being done: > > switch (dev->chipset) { > case 0xc8: > obj_class = NVC8_3D_CLASS; > break; > case 0xc1: > obj_class = NVC1_3D_CLASS; > break; > default: > obj_class = NVC0_3D_CLASS; > break; > } > > Shouldn't we try to be consistent with this more local example instead? Which is why I didn't insist. The situation with nvcx is a little different -- nvc8 (GF110) and nvc1 (GF108) are special, but e.g. nvce (GF114) and nvcf (GF116) want the nvc0 class. OTOH you're using >= 0xea as the metric for selecting SM35, so I was just pointing out the inconsistency. Of course there needn't be a 1:1 mapping between these things, and the likelihood of another 0xex chipset being released is fairly low. So: Reviewed-by: Ilia Mirkin <imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org> ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/2] nvc0: use SM35 ISA with GK20A [not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-05-27 4:59 ` [PATCH 1/2] nvc0: add GK20A 3D class Alexandre Courbot @ 2014-05-27 4:59 ` Alexandre Courbot [not found] ` <1401166783-24086-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-05-27 7:03 ` [PATCH v2 0/2] nvc0: support for GK20A (Tegra K1) Alexandre Courbot 2014-05-27 7:03 ` [PATCH v2 1/2] nvc0: add GK20A 3D class Alexandre Courbot 3 siblings, 1 reply; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 4:59 UTC (permalink / raw) To: Ilia Mirkin Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected. Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- 3 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index bbb89d97932e..aab857ee7e4f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol #define NVISA_GF100_CHIPSET_C0 0xc0 #define NVISA_GF100_CHIPSET_D0 0xd0 #define NVISA_GK104_CHIPSET 0xe0 +#define NVISA_GK20A_CHIPSET 0xea #define NVISA_GK110_CHIPSET 0xf0 #define NVISA_GM107_CHIPSET 0x110 diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index b1f76cf80432..f69e6a183e19 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET) + if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp index 064e7a2c63f9..8212bfd9555e 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset != NVISA_GK20A_CHIPSET) { + *code = (const uint32_t *)&gk104_builtin_code[0]; + *size = sizeof(gk104_builtin_code); + break; + } + /* fall-through for GK20A */ case 0xf0: case 0x100: *code = (const uint32_t *)&gk110_builtin_code[0]; @@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const switch (chipset & ~0xf) { case 0xe0: - return gk104_builtin_offsets[builtin]; + if (chipset != NVISA_GK20A_CHIPSET) + return gk104_builtin_offsets[builtin]; + /* fall-through for GK20A */ case 0xf0: case 0x100: return gk110_builtin_offsets[builtin]; -- 1.9.3 ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <1401166783-24086-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH 2/2] nvc0: use SM35 ISA with GK20A [not found] ` <1401166783-24086-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-05-27 5:26 ` Ilia Mirkin [not found] ` <CAKb7Uvi_-DrhjFPS+D=P71bF+V5K21xKYK_+FhxmvX-Kyyf89Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 12+ messages in thread From: Ilia Mirkin @ 2014-05-27 5:26 UTC (permalink / raw) To: Alexandre Courbot Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Alexandre Courbot On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use > the GK110 path when this chip is detected. > > Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- > src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- > 3 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > index bbb89d97932e..aab857ee7e4f 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol > #define NVISA_GF100_CHIPSET_C0 0xc0 > #define NVISA_GF100_CHIPSET_D0 0xd0 > #define NVISA_GK104_CHIPSET 0xe0 > +#define NVISA_GK20A_CHIPSET 0xea > #define NVISA_GK110_CHIPSET 0xf0 > #define NVISA_GM107_CHIPSET 0x110 > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > index b1f76cf80432..f69e6a183e19 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) > CodeEmitter * > TargetNVC0::getCodeEmitter(Program::Type type) > { > - if (chipset >= NVISA_GK110_CHIPSET) > + if (chipset >= NVISA_GK20A_CHIPSET) > return createCodeEmitterGK110(type); > return createCodeEmitterNVC0(type); > } As mentioned on IRC, you also need to update TargetNVC0::getFileSize to return 255 GPRs, since that value is presumably ISA-specific. You could, at that point, get rid of the GK110_CHIPSET define. Eventually all that stuff needs to be nuked and replaced with an 'isa' property. But you don't have to do that. > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > index 064e7a2c63f9..8212bfd9555e 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const > { > switch (chipset & ~0xf) { > case 0xe0: > - *code = (const uint32_t *)&gk104_builtin_code[0]; > - *size = sizeof(gk104_builtin_code); > - break; > + if (chipset != NVISA_GK20A_CHIPSET) { You change the code emitter if chipset >= GK20A. Might as well be consistent here and below. > + *code = (const uint32_t *)&gk104_builtin_code[0]; > + *size = sizeof(gk104_builtin_code); > + break; > + } > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > *code = (const uint32_t *)&gk110_builtin_code[0]; > @@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const > > switch (chipset & ~0xf) { > case 0xe0: > - return gk104_builtin_offsets[builtin]; > + if (chipset != NVISA_GK20A_CHIPSET) > + return gk104_builtin_offsets[builtin]; > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > return gk110_builtin_offsets[builtin]; > -- > 1.9.3 > ^ permalink raw reply [flat|nested] 12+ messages in thread
[parent not found: <CAKb7Uvi_-DrhjFPS+D=P71bF+V5K21xKYK_+FhxmvX-Kyyf89Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH 2/2] nvc0: use SM35 ISA with GK20A [not found] ` <CAKb7Uvi_-DrhjFPS+D=P71bF+V5K21xKYK_+FhxmvX-Kyyf89Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2014-05-27 6:51 ` Alexandre Courbot 0 siblings, 0 replies; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 6:51 UTC (permalink / raw) To: Ilia Mirkin Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Alexandre Courbot On 05/27/2014 02:26 PM, Ilia Mirkin wrote: > On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: >> GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use >> the GK110 path when this chip is detected. >> >> Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> >> --- >> src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 + >> src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- >> src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 13 +++++++++---- >> 3 files changed, 11 insertions(+), 5 deletions(-) >> >> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h >> index bbb89d97932e..aab857ee7e4f 100644 >> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h >> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h >> @@ -91,6 +91,7 @@ struct nv50_ir_prog_symbol >> #define NVISA_GF100_CHIPSET_C0 0xc0 >> #define NVISA_GF100_CHIPSET_D0 0xd0 >> #define NVISA_GK104_CHIPSET 0xe0 >> +#define NVISA_GK20A_CHIPSET 0xea >> #define NVISA_GK110_CHIPSET 0xf0 >> #define NVISA_GM107_CHIPSET 0x110 >> >> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp >> index b1f76cf80432..f69e6a183e19 100644 >> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp >> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp >> @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) >> CodeEmitter * >> TargetNVC0::getCodeEmitter(Program::Type type) >> { >> - if (chipset >= NVISA_GK110_CHIPSET) >> + if (chipset >= NVISA_GK20A_CHIPSET) >> return createCodeEmitterGK110(type); >> return createCodeEmitterNVC0(type); >> } > > As mentioned on IRC, you also need to update TargetNVC0::getFileSize > to return 255 GPRs, since that value is presumably ISA-specific. You > could, at that point, get rid of the GK110_CHIPSET define. Will do. > Eventually > all that stuff needs to be nuked and replaced with an 'isa' property. > But you don't have to do that. > >> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp >> index 064e7a2c63f9..8212bfd9555e 100644 >> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp >> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp >> @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const >> { >> switch (chipset & ~0xf) { >> case 0xe0: >> - *code = (const uint32_t *)&gk104_builtin_code[0]; >> - *size = sizeof(gk104_builtin_code); >> - break; >> + if (chipset != NVISA_GK20A_CHIPSET) { > > You change the code emitter if chipset >= GK20A. Might as well be > consistent here and below. Sure. ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 0/2] nvc0: support for GK20A (Tegra K1) [not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-05-27 4:59 ` [PATCH 1/2] nvc0: add GK20A 3D class Alexandre Courbot 2014-05-27 4:59 ` [PATCH 2/2] nvc0: use SM35 ISA with GK20A Alexandre Courbot @ 2014-05-27 7:03 ` Alexandre Courbot 2014-05-27 7:03 ` [PATCH v2 1/2] nvc0: add GK20A 3D class Alexandre Courbot 3 siblings, 0 replies; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 7:03 UTC (permalink / raw) To: Ilia Mirkin, Ken Adams, Terje Bergstrom, Thierry Reding Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w, Alexandre Courbot The following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1). GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers. Changes since v1: - Update TargetNVC0::getFileSize() to return the right number of GPR - Remove definition for unneeded NVISA_GK110_CHIPSET - Use consistent comparison scheme in nv50_ir_emit_nvc0.cpp Alexandre Courbot (2): nvc0: add GK20A 3D class nvc0: use SM35 ISA with GK20A src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 5 files changed, 21 insertions(+), 8 deletions(-) -- 1.9.3 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 1/2] nvc0: add GK20A 3D class [not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> ` (2 preceding siblings ...) 2014-05-27 7:03 ` [PATCH v2 0/2] nvc0: support for GK20A (Tegra K1) Alexandre Courbot @ 2014-05-27 7:03 ` Alexandre Courbot 3 siblings, 0 replies; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 7:03 UTC (permalink / raw) To: Ilia Mirkin, Ken Adams, Terje Bergstrom, Thierry Reding Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, linux-tegra-u79uwXL29TY76Z2rM5mHXA, gnurou-Re5JQEeQqe8AvxtiuMwx3w, Alexandre Courbot GK20A is mostly compatible with GK104, but features a new 3D class. Add it to the relevant header and use it when GK20A is detected. Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- src/gallium/drivers/nouveau/nv_object.xml.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nv_object.xml.h b/src/gallium/drivers/nouveau/nv_object.xml.h index 4c93e6564838..0a0e187dc028 100644 --- a/src/gallium/drivers/nouveau/nv_object.xml.h +++ b/src/gallium/drivers/nouveau/nv_object.xml.h @@ -190,6 +190,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC8_3D_CLASS 0x00009297 #define NVE4_3D_CLASS 0x0000a097 #define NVF0_3D_CLASS 0x0000a197 +#define NVEA_3D_CLASS 0x0000a297 #define GM107_3D_CLASS 0x0000b097 #define NV50_2D_CLASS 0x0000502d #define NVC0_2D_CLASS 0x0000902d diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index cccfe2bba23d..95e5ef81cd79 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -702,7 +702,14 @@ nvc0_screen_create(struct nouveau_device *dev) obj_class = NVF0_3D_CLASS; break; case 0xe0: - obj_class = NVE4_3D_CLASS; + switch (dev->chipset) { + case 0xea: + obj_class = NVEA_3D_CLASS; + break; + default: + obj_class = NVE4_3D_CLASS; + break; + } break; case 0xd0: obj_class = NVC8_3D_CLASS; -- 1.9.3 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A 2014-05-27 4:59 [PATCH 0/2] nvc0: support for GK20A (Tegra K1) Alexandre Courbot [not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-05-27 7:03 ` Alexandre Courbot [not found] ` <1401174182-2182-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 1 sibling, 1 reply; 12+ messages in thread From: Alexandre Courbot @ 2014-05-27 7:03 UTC (permalink / raw) To: Ilia Mirkin, Ken Adams, Terje Bergstrom, Thierry Reding Cc: linux-tegra, nouveau, gnurou, mesa-dev GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use the GK110 path when this chip is detected. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h index bbb89d97932e..f829aac0bcc2 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h @@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol #define NVISA_GF100_CHIPSET_C0 0xc0 #define NVISA_GF100_CHIPSET_D0 0xd0 #define NVISA_GK104_CHIPSET 0xe0 -#define NVISA_GK110_CHIPSET 0xf0 +#define NVISA_GK20A_CHIPSET 0xea #define NVISA_GM107_CHIPSET 0x110 struct nv50_ir_prog_info diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index b1f76cf80432..f69e6a183e19 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) CodeEmitter * TargetNVC0::getCodeEmitter(Program::Type type) { - if (chipset >= NVISA_GK110_CHIPSET) + if (chipset >= NVISA_GK20A_CHIPSET) return createCodeEmitterGK110(type); return createCodeEmitterNVC0(type); } diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp index 064e7a2c63f9..963b6e47ddfc 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const { switch (chipset & ~0xf) { case 0xe0: - *code = (const uint32_t *)&gk104_builtin_code[0]; - *size = sizeof(gk104_builtin_code); - break; + if (chipset < NVISA_GK20A_CHIPSET) { + *code = (const uint32_t *)&gk104_builtin_code[0]; + *size = sizeof(gk104_builtin_code); + break; + } + /* fall-through for GK20A */ case 0xf0: case 0x100: *code = (const uint32_t *)&gk110_builtin_code[0]; @@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const switch (chipset & ~0xf) { case 0xe0: - return gk104_builtin_offsets[builtin]; + if (chipset < NVISA_GK20A_CHIPSET) + return gk104_builtin_offsets[builtin]; + /* fall-through for GK20A */ case 0xf0: case 0x100: return gk110_builtin_offsets[builtin]; @@ -235,7 +240,7 @@ TargetNVC0::getFileSize(DataFile file) const { switch (file) { case FILE_NULL: return 0; - case FILE_GPR: return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63; + case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63; case FILE_PREDICATE: return 7; case FILE_FLAGS: return 1; case FILE_ADDRESS: return 0; -- 1.9.3 ^ permalink raw reply related [flat|nested] 12+ messages in thread
[parent not found: <1401174182-2182-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A [not found] ` <1401174182-2182-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> @ 2014-05-27 15:49 ` Ilia Mirkin 0 siblings, 0 replies; 12+ messages in thread From: Ilia Mirkin @ 2014-05-27 15:49 UTC (permalink / raw) To: Alexandre Courbot Cc: Ken Adams, Terje Bergstrom, Thierry Reding, nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Alexandre Courbot On Tue, May 27, 2014 at 3:03 AM, Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: > GK20A is mostly compatible with GK104, but uses the SM35 ISA. Use > the GK110 path when this chip is detected. > > Signed-off-by: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Reviewed-by: Ilia Mirkin <imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org> > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 2 +- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- > .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 15 ++++++++++----- > 3 files changed, 12 insertions(+), 7 deletions(-) > > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > index bbb89d97932e..f829aac0bcc2 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h > @@ -91,7 +91,7 @@ struct nv50_ir_prog_symbol > #define NVISA_GF100_CHIPSET_C0 0xc0 > #define NVISA_GF100_CHIPSET_D0 0xd0 > #define NVISA_GK104_CHIPSET 0xe0 > -#define NVISA_GK110_CHIPSET 0xf0 > +#define NVISA_GK20A_CHIPSET 0xea > #define NVISA_GM107_CHIPSET 0x110 > > struct nv50_ir_prog_info > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > index b1f76cf80432..f69e6a183e19 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp > @@ -3027,7 +3027,7 @@ TargetNVC0::createCodeEmitterNVC0(Program::Type type) > CodeEmitter * > TargetNVC0::getCodeEmitter(Program::Type type) > { > - if (chipset >= NVISA_GK110_CHIPSET) > + if (chipset >= NVISA_GK20A_CHIPSET) > return createCodeEmitterGK110(type); > return createCodeEmitterNVC0(type); > } > diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > index 064e7a2c63f9..963b6e47ddfc 100644 > --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp > @@ -49,9 +49,12 @@ TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const > { > switch (chipset & ~0xf) { > case 0xe0: > - *code = (const uint32_t *)&gk104_builtin_code[0]; > - *size = sizeof(gk104_builtin_code); > - break; > + if (chipset < NVISA_GK20A_CHIPSET) { > + *code = (const uint32_t *)&gk104_builtin_code[0]; > + *size = sizeof(gk104_builtin_code); > + break; > + } > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > *code = (const uint32_t *)&gk110_builtin_code[0]; > @@ -71,7 +74,9 @@ TargetNVC0::getBuiltinOffset(int builtin) const > > switch (chipset & ~0xf) { > case 0xe0: > - return gk104_builtin_offsets[builtin]; > + if (chipset < NVISA_GK20A_CHIPSET) > + return gk104_builtin_offsets[builtin]; > + /* fall-through for GK20A */ > case 0xf0: > case 0x100: > return gk110_builtin_offsets[builtin]; > @@ -235,7 +240,7 @@ TargetNVC0::getFileSize(DataFile file) const > { > switch (file) { > case FILE_NULL: return 0; > - case FILE_GPR: return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63; > + case FILE_GPR: return (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63; > case FILE_PREDICATE: return 7; > case FILE_FLAGS: return 1; > case FILE_ADDRESS: return 0; > -- > 1.9.3 > ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2014-05-27 15:49 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
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2014-05-27 4:59 [PATCH 0/2] nvc0: support for GK20A (Tegra K1) Alexandre Courbot
[not found] ` <1401166783-24086-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-27 4:59 ` [PATCH 1/2] nvc0: add GK20A 3D class Alexandre Courbot
[not found] ` <1401166783-24086-2-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-27 5:29 ` Ilia Mirkin
[not found] ` <CAKb7Uvjvo=9u-mSH01AHidOBS_6cE88kpy+H=QoJQprtLekvKg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-05-27 6:35 ` Alexandre Courbot
[not found] ` <53843236.4030508-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-27 15:48 ` Ilia Mirkin
2014-05-27 4:59 ` [PATCH 2/2] nvc0: use SM35 ISA with GK20A Alexandre Courbot
[not found] ` <1401166783-24086-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-27 5:26 ` Ilia Mirkin
[not found] ` <CAKb7Uvi_-DrhjFPS+D=P71bF+V5K21xKYK_+FhxmvX-Kyyf89Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-05-27 6:51 ` Alexandre Courbot
2014-05-27 7:03 ` [PATCH v2 0/2] nvc0: support for GK20A (Tegra K1) Alexandre Courbot
2014-05-27 7:03 ` [PATCH v2 1/2] nvc0: add GK20A 3D class Alexandre Courbot
2014-05-27 7:03 ` [PATCH v2 2/2] nvc0: use SM35 ISA with GK20A Alexandre Courbot
[not found] ` <1401174182-2182-3-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-05-27 15:49 ` Ilia Mirkin
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