From: Julien Grall <julien.grall@linaro.org>
To: Stefano Stabellini <stefano.stabellini@eu.citrix.com>,
xen-devel@lists.xensource.com
Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com
Subject: Re: [PATCH 2/2] xen/arm: observe itarget setting in vgic_enable_irqs and vgic_disable_irqs
Date: Tue, 27 May 2014 17:54:24 +0100 [thread overview]
Message-ID: <5384C340.6090904@linaro.org> (raw)
In-Reply-To: <1401041192-20424-2-git-send-email-stefano.stabellini@eu.citrix.com>
Hi Stefano,
On 05/25/2014 07:06 PM, Stefano Stabellini wrote:
> while ( (i = find_next_bit(&mask, 32, i)) < 32 ) {
> irq = i + (32 * n);
> - p = irq_to_pending(v, irq);
> + rank = vgic_irq_rank(v, 1, irq/32);
> + vgic_lock_rank(v, rank);
> + if ( irq >= 32 )
> + {
> + target = rank->itargets[(irq%32)/4] >> (8*(irq % 4));
> + target &= 0xff;
> + v_target = v->domain->vcpu[target];
Without looking to the target stuff (see comment on patch #1), I don't
need to do a specific case for SPIs.
It will avoid diverging following the IRQ type.
Regards,
--
Julien Grall
next prev parent reply other threads:[~2014-05-27 16:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-25 18:06 [PATCH 0/2] vgic emulation and GICD_ITARGETSR Stefano Stabellini
2014-05-25 18:06 ` [PATCH 1/2] xen/arm: add a warning if the guest asks for SPI delivery to vcpu != 0 Stefano Stabellini
2014-05-25 19:01 ` Julien Grall
2014-05-27 16:24 ` Stefano Stabellini
2014-05-25 18:06 ` [PATCH 2/2] xen/arm: observe itarget setting in vgic_enable_irqs and vgic_disable_irqs Stefano Stabellini
2014-05-27 16:54 ` Julien Grall [this message]
2014-05-27 17:02 ` Stefano Stabellini
2014-05-27 17:09 ` Julien Grall
2014-05-27 17:10 ` Julien Grall
2014-06-03 14:24 ` Stefano Stabellini
2014-05-28 13:38 ` Ian Campbell
2014-06-03 14:03 ` Stefano Stabellini
2014-05-28 13:33 ` [PATCH 0/2] vgic emulation and GICD_ITARGETSR Ian Campbell
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