Re: [PATCH 2/2] xen/arm: observe itarget setting in vgic_enable_irqs and vgic_disable_irqs

[Julien Grall <julien.grall@linaro.org>]

On 05/27/2014 06:02 PM, Stefano Stabellini wrote:
> On Tue, 27 May 2014, Julien Grall wrote:
>> Hi Stefano,
>>
>> On 05/25/2014 07:06 PM, Stefano Stabellini wrote:
>>>      while ( (i = find_next_bit(&mask, 32, i)) < 32 ) {
>>>          irq = i + (32 * n);
>>> -        p = irq_to_pending(v, irq);
>>> +        rank = vgic_irq_rank(v, 1, irq/32);
>>> +        vgic_lock_rank(v, rank);
>>> +        if ( irq >= 32 )
>>> +        {
>>> +            target = rank->itargets[(irq%32)/4] >> (8*(irq % 4));
>>> +            target &= 0xff;
>>> +            v_target = v->domain->vcpu[target];
>>
>> Without looking to the target stuff (see comment on patch #1), I don't
>> need to do a specific case for SPIs.
>>
>> It will avoid diverging following the IRQ type.
> 
> Sooner or later we'll implement SPI delivery to vcpu != 0. When we do
> we'll actually need this patch, that is correct even without SPI
> delivery to vcpu != 0.
> 

To be clear, I didn't say this patch was not useful. I just say we can
merge the code and do use the same path for non-SPIs.

Regards,

-- 
Julien Grall