* [PATCH] pinctrl: st: Fix irqmux handler
@ 2014-06-20 11:34 ` Maxime COQUELIN
0 siblings, 0 replies; 6+ messages in thread
From: Maxime COQUELIN @ 2014-06-20 11:34 UTC (permalink / raw)
To: linux-arm-kernel
st_gpio_irqmux_handler() reads the status register to find out
which banks inside the controller have pending IRQs.
For each banks having pending IRQs, it calls the corresponding handler.
Problem is that current code restricts the number of possible banks inside the
controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
inside a bank, so it shouldn't be used here.
On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
last banks (PIO18 & PIO19) aren't handled.
This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
controller.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: <stable@vger.kernel.org> #v3.15+
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
drivers/pinctrl/pinctrl-st.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 1bd6363bc9..9f43916 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
status = readl(info->irqmux_base);
- for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
+ for_each_set_bit(n, &status, info->nbanks)
__gpio_irq_handler(&info->banks[n]);
chained_irq_exit(chip, desc);
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] pinctrl: st: Fix irqmux handler
@ 2014-06-20 11:34 ` Maxime COQUELIN
0 siblings, 0 replies; 6+ messages in thread
From: Maxime COQUELIN @ 2014-06-20 11:34 UTC (permalink / raw)
To: Linus Walleij, Srinivas Kandagatla, linux-arm-kernel,
linux-kernel, stable
Cc: kernel, patrice.chotard, maxime.coquelin
st_gpio_irqmux_handler() reads the status register to find out
which banks inside the controller have pending IRQs.
For each banks having pending IRQs, it calls the corresponding handler.
Problem is that current code restricts the number of possible banks inside the
controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
inside a bank, so it shouldn't be used here.
On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
last banks (PIO18 & PIO19) aren't handled.
This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
controller.
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: <stable@vger.kernel.org> #v3.15+
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
drivers/pinctrl/pinctrl-st.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 1bd6363bc9..9f43916 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
status = readl(info->irqmux_base);
- for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
+ for_each_set_bit(n, &status, info->nbanks)
__gpio_irq_handler(&info->banks[n]);
chained_irq_exit(chip, desc);
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] pinctrl: st: Fix irqmux handler
2014-06-20 11:34 ` Maxime COQUELIN
@ 2014-06-20 11:38 ` Srinivas Kandagatla
-1 siblings, 0 replies; 6+ messages in thread
From: Srinivas Kandagatla @ 2014-06-20 11:38 UTC (permalink / raw)
To: linux-arm-kernel
On 20/06/14 12:34, Maxime COQUELIN wrote:
> st_gpio_irqmux_handler() reads the status register to find out
> which banks inside the controller have pending IRQs.
> For each banks having pending IRQs, it calls the corresponding handler.
>
> Problem is that current code restricts the number of possible banks inside the
> controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
> inside a bank, so it shouldn't be used here.
You are right.
Good find.
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>
> On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
> last banks (PIO18 & PIO19) aren't handled.
>
> This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
> controller.
>
> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: <stable@vger.kernel.org> #v3.15+
> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 1bd6363bc9..9f43916 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
>
> status = readl(info->irqmux_base);
>
> - for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
> + for_each_set_bit(n, &status, info->nbanks)
> __gpio_irq_handler(&info->banks[n]);
>
> chained_irq_exit(chip, desc);
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] pinctrl: st: Fix irqmux handler
@ 2014-06-20 11:38 ` Srinivas Kandagatla
0 siblings, 0 replies; 6+ messages in thread
From: Srinivas Kandagatla @ 2014-06-20 11:38 UTC (permalink / raw)
To: Maxime COQUELIN, Linus Walleij, Srinivas Kandagatla,
linux-arm-kernel, linux-kernel, stable
Cc: kernel, patrice.chotard
On 20/06/14 12:34, Maxime COQUELIN wrote:
> st_gpio_irqmux_handler() reads the status register to find out
> which banks inside the controller have pending IRQs.
> For each banks having pending IRQs, it calls the corresponding handler.
>
> Problem is that current code restricts the number of possible banks inside the
> controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
> inside a bank, so it shouldn't be used here.
You are right.
Good find.
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>
> On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
> last banks (PIO18 & PIO19) aren't handled.
>
> This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
> controller.
>
> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: <stable@vger.kernel.org> #v3.15+
> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
> ---
> drivers/pinctrl/pinctrl-st.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
> index 1bd6363bc9..9f43916 100644
> --- a/drivers/pinctrl/pinctrl-st.c
> +++ b/drivers/pinctrl/pinctrl-st.c
> @@ -1431,7 +1431,7 @@ static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
>
> status = readl(info->irqmux_base);
>
> - for_each_set_bit(n, &status, ST_GPIO_PINS_PER_BANK)
> + for_each_set_bit(n, &status, info->nbanks)
> __gpio_irq_handler(&info->banks[n]);
>
> chained_irq_exit(chip, desc);
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] pinctrl: st: Fix irqmux handler
2014-06-20 11:34 ` Maxime COQUELIN
@ 2014-07-07 14:59 ` Linus Walleij
-1 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2014-07-07 14:59 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jun 20, 2014 at 1:34 PM, Maxime COQUELIN <maxime.coquelin@st.com> wrote:
> st_gpio_irqmux_handler() reads the status register to find out
> which banks inside the controller have pending IRQs.
> For each banks having pending IRQs, it calls the corresponding handler.
>
> Problem is that current code restricts the number of possible banks inside the
> controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
> inside a bank, so it shouldn't be used here.
>
> On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
> last banks (PIO18 & PIO19) aren't handled.
>
> This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
> controller.
>
> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: <stable@vger.kernel.org> #v3.15+
> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Patch applied for fixes with Srinivas ACK.
Thanks!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] pinctrl: st: Fix irqmux handler
@ 2014-07-07 14:59 ` Linus Walleij
0 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2014-07-07 14:59 UTC (permalink / raw)
To: Maxime COQUELIN
Cc: Srinivas Kandagatla, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, stable, kernel, Patrice CHOTARD
On Fri, Jun 20, 2014 at 1:34 PM, Maxime COQUELIN <maxime.coquelin@st.com> wrote:
> st_gpio_irqmux_handler() reads the status register to find out
> which banks inside the controller have pending IRQs.
> For each banks having pending IRQs, it calls the corresponding handler.
>
> Problem is that current code restricts the number of possible banks inside the
> controller to ST_GPIO_PINS_PER_BANK. This define represents the number of pins
> inside a bank, so it shouldn't be used here.
>
> On STiH407, PIO_FRONT0 controller has 10 banks, so IRQs pending in the two
> last banks (PIO18 & PIO19) aren't handled.
>
> This patch replace ST_GPIO_PINS_PER_BANK by the number of banks inside the
> controller.
>
> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: <stable@vger.kernel.org> #v3.15+
> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Patch applied for fixes with Srinivas ACK.
Thanks!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-07-07 14:59 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-06-20 11:34 [PATCH] pinctrl: st: Fix irqmux handler Maxime COQUELIN
2014-06-20 11:34 ` Maxime COQUELIN
2014-06-20 11:38 ` Srinivas Kandagatla
2014-06-20 11:38 ` Srinivas Kandagatla
2014-07-07 14:59 ` Linus Walleij
2014-07-07 14:59 ` Linus Walleij
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.