* [PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-06-25 18:02 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-06-25 18:02 UTC (permalink / raw)
To: linux-arm-kernel
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..934aa9d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-06-25 18:02 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-06-25 18:02 UTC (permalink / raw)
To: devicetree, linux-pci, linux-omap, paul, tony, linux, rnayak,
linux-arm-kernel, linux-kernel
Cc: kishon
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..934aa9d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
2014-06-25 18:02 ` Kishon Vijay Abraham I
(?)
@ 2014-07-03 8:07 ` Rajendra Nayak
-1 siblings, 0 replies; 31+ messages in thread
From: Rajendra Nayak @ 2014-07-03 8:07 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, linux-pci, linux-omap, paul, tony, linux,
linux-arm-kernel, linux-kernel
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..934aa9d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
The TRM tells me it belongs to 'pcie_clkdm' instead. Can you please recheck?
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> pcie1 */
There seems to be a slave port on l3_init as well which seems to be missing?
Refer to 'Figure 24-157. PCIe Controllers Integration' of TRM version P.
regards,
Rajendra
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-03 8:07 ` Rajendra Nayak
0 siblings, 0 replies; 31+ messages in thread
From: Rajendra Nayak @ 2014-07-03 8:07 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..934aa9d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
The TRM tells me it belongs to 'pcie_clkdm' instead. Can you please recheck?
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> pcie1 */
There seems to be a slave port on l3_init as well which seems to be missing?
Refer to 'Figure 24-157. PCIe Controllers Integration' of TRM version P.
regards,
Rajendra
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH 2/2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-03 8:07 ` Rajendra Nayak
0 siblings, 0 replies; 31+ messages in thread
From: Rajendra Nayak @ 2014-07-03 8:07 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, linux-pci, linux-omap, paul, tony, linux,
linux-arm-kernel, linux-kernel
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..934aa9d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
The TRM tells me it belongs to 'pcie_clkdm' instead. Can you please recheck?
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> pcie1 */
There seems to be a slave port on l3_init as well which seems to be missing?
Refer to 'Figure 24-157. PCIe Controllers Integration' of TRM version P.
regards,
Rajendra
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
2014-06-25 18:02 ` Kishon Vijay Abraham I
(?)
@ 2014-07-09 9:02 ` Kishon Vijay Abraham I
-1 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-09 9:02 UTC (permalink / raw)
To: devicetree, linux-pci, linux-omap, paul, tony, linux, rnayak,
linux-arm-kernel, linux-kernel
Cc: kishon
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Changes from v1:
* changed the clock domain to "pcie_clkdm"
* Added PCIe as a slave port for l3_main.
Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..2f37ca8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main_1 -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l3_main_1__pcie1,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l3_main_1__pcie2,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-09 9:02 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-09 9:02 UTC (permalink / raw)
To: linux-arm-kernel
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Changes from v1:
* changed the clock domain to "pcie_clkdm"
* Added PCIe as a slave port for l3_main.
Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..2f37ca8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main_1 -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l3_main_1__pcie1,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l3_main_1__pcie2,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-09 9:02 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-09 9:02 UTC (permalink / raw)
To: devicetree, linux-pci, linux-omap, paul, tony, linux, rnayak,
linux-arm-kernel, linux-kernel
Cc: kishon
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Changes from v1:
* changed the clock domain to "pcie_clkdm"
* Added PCIe as a slave port for l3_main.
Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..2f37ca8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main_1 -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l3_main_1__pcie1,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l3_main_1__pcie2,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
2014-07-09 9:02 ` Kishon Vijay Abraham I
(?)
@ 2014-07-09 11:02 ` Rajendra Nayak
-1 siblings, 0 replies; 31+ messages in thread
From: Rajendra Nayak @ 2014-07-09 11:02 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, linux-pci, linux-omap, paul, tony, linux,
linux-arm-kernel, linux-kernel
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Changes from v1:
> * changed the clock domain to "pcie_clkdm"
> * Added PCIe as a slave port for l3_main.
Looks good to me,
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>
> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..2f37ca8 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l3_main_1 -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l3_main_1__pcie1,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l3_main_1__pcie2,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-09 11:02 ` Rajendra Nayak
0 siblings, 0 replies; 31+ messages in thread
From: Rajendra Nayak @ 2014-07-09 11:02 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Changes from v1:
> * changed the clock domain to "pcie_clkdm"
> * Added PCIe as a slave port for l3_main.
Looks good to me,
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>
> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..2f37ca8 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l3_main_1 -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l3_main_1__pcie1,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l3_main_1__pcie2,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-09 11:02 ` Rajendra Nayak
0 siblings, 0 replies; 31+ messages in thread
From: Rajendra Nayak @ 2014-07-09 11:02 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: devicetree, linux-pci, linux-omap, paul, tony, linux,
linux-arm-kernel, linux-kernel
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Paul Walmsley <paul@pwsan.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> Changes from v1:
> * changed the clock domain to "pcie_clkdm"
> * Added PCIe as a slave port for l3_main.
Looks good to me,
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>
> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..2f37ca8 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l3_main_1 -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l3_main_1__pcie1,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l3_main_1__pcie2,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
2014-07-09 11:02 ` Rajendra Nayak
(?)
@ 2014-07-14 10:34 ` Kishon Vijay Abraham I
-1 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:34 UTC (permalink / raw)
To: Rajendra Nayak, paul
Cc: devicetree, linux-pci, linux-omap, tony, linux, linux-arm-kernel,
linux-kernel
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: Paul Walmsley <paul@pwsan.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> Changes from v1:
>> * changed the clock domain to "pcie_clkdm"
>> * Added PCIe as a slave port for l3_main.
>
> Looks good to me,
> Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Paul,
Can you pick this one?
Thanks
Kishon
>
>>
>> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>>
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 6ff40a6..2f37ca8 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> };
>>
>> /*
>> + * 'PCIE' class
>> + *
>> + */
>> +
>> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
>> + .name = "pcie",
>> +};
>> +
>> +/* pcie1 */
>> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
>> + .name = "pcie1",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/* pcie2 */
>> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
>> + .name = "pcie2",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/*
>> * 'PCIE PHY' class
>> *
>> */
>> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
>> .user = OCP_USER_MPU | OCP_USER_SDMA,
>> };
>>
>> +/* l3_main_1 -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> /* l4_cfg -> pcie1 phy */
>> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
>> .master = &dra7xx_l4_cfg_hwmod,
>> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>> &dra7xx_l4_cfg__mpu,
>> &dra7xx_l4_cfg__ocp2scp1,
>> &dra7xx_l4_cfg__ocp2scp3,
>> + &dra7xx_l3_main_1__pcie1,
>> + &dra7xx_l4_cfg__pcie1,
>> + &dra7xx_l3_main_1__pcie2,
>> + &dra7xx_l4_cfg__pcie2,
>> &dra7xx_l4_cfg__pcie1_phy,
>> &dra7xx_l4_cfg__pcie2_phy,
>> &dra7xx_l3_main_1__qspi,
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-14 10:34 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:34 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: Paul Walmsley <paul@pwsan.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> Changes from v1:
>> * changed the clock domain to "pcie_clkdm"
>> * Added PCIe as a slave port for l3_main.
>
> Looks good to me,
> Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Paul,
Can you pick this one?
Thanks
Kishon
>
>>
>> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>>
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 6ff40a6..2f37ca8 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> };
>>
>> /*
>> + * 'PCIE' class
>> + *
>> + */
>> +
>> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
>> + .name = "pcie",
>> +};
>> +
>> +/* pcie1 */
>> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
>> + .name = "pcie1",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/* pcie2 */
>> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
>> + .name = "pcie2",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/*
>> * 'PCIE PHY' class
>> *
>> */
>> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
>> .user = OCP_USER_MPU | OCP_USER_SDMA,
>> };
>>
>> +/* l3_main_1 -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> /* l4_cfg -> pcie1 phy */
>> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
>> .master = &dra7xx_l4_cfg_hwmod,
>> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>> &dra7xx_l4_cfg__mpu,
>> &dra7xx_l4_cfg__ocp2scp1,
>> &dra7xx_l4_cfg__ocp2scp3,
>> + &dra7xx_l3_main_1__pcie1,
>> + &dra7xx_l4_cfg__pcie1,
>> + &dra7xx_l3_main_1__pcie2,
>> + &dra7xx_l4_cfg__pcie2,
>> &dra7xx_l4_cfg__pcie1_phy,
>> &dra7xx_l4_cfg__pcie2_phy,
>> &dra7xx_l3_main_1__qspi,
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-14 10:34 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-14 10:34 UTC (permalink / raw)
To: Rajendra Nayak, paul
Cc: devicetree, linux-pci, linux-omap, tony, linux, linux-arm-kernel,
linux-kernel
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>
>> Cc: Tony Lindgren <tony@atomide.com>
>> Cc: Russell King <linux@arm.linux.org.uk>
>> Cc: Paul Walmsley <paul@pwsan.com>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> Changes from v1:
>> * changed the clock domain to "pcie_clkdm"
>> * Added PCIe as a slave port for l3_main.
>
> Looks good to me,
> Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Paul,
Can you pick this one?
Thanks
Kishon
>
>>
>> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>>
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 6ff40a6..2f37ca8 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> };
>>
>> /*
>> + * 'PCIE' class
>> + *
>> + */
>> +
>> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
>> + .name = "pcie",
>> +};
>> +
>> +/* pcie1 */
>> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
>> + .name = "pcie1",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/* pcie2 */
>> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
>> + .name = "pcie2",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/*
>> * 'PCIE PHY' class
>> *
>> */
>> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
>> .user = OCP_USER_MPU | OCP_USER_SDMA,
>> };
>>
>> +/* l3_main_1 -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> /* l4_cfg -> pcie1 phy */
>> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
>> .master = &dra7xx_l4_cfg_hwmod,
>> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>> &dra7xx_l4_cfg__mpu,
>> &dra7xx_l4_cfg__ocp2scp1,
>> &dra7xx_l4_cfg__ocp2scp3,
>> + &dra7xx_l3_main_1__pcie1,
>> + &dra7xx_l4_cfg__pcie1,
>> + &dra7xx_l3_main_1__pcie2,
>> + &dra7xx_l4_cfg__pcie2,
>> &dra7xx_l4_cfg__pcie1_phy,
>> &dra7xx_l4_cfg__pcie2_phy,
>> &dra7xx_l3_main_1__qspi,
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
2014-07-14 10:34 ` Kishon Vijay Abraham I
@ 2014-07-15 20:13 ` Paul Walmsley
-1 siblings, 0 replies; 31+ messages in thread
From: Paul Walmsley @ 2014-07-15 20:13 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Rajendra Nayak, devicetree, linux-pci, linux-omap, tony, linux,
linux-arm-kernel, linux-kernel
On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> > On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> >> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
> >>
> >> Cc: Tony Lindgren <tony@atomide.com>
> >> Cc: Russell King <linux@arm.linux.org.uk>
> >> Cc: Paul Walmsley <paul@pwsan.com>
> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> ---
> >> Changes from v1:
> >> * changed the clock domain to "pcie_clkdm"
> >> * Added PCIe as a slave port for l3_main.
> >
> > Looks good to me,
> > Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>
> Paul,
>
> Can you pick this one?
Yep, queued for 3.17.
- Paul
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-15 20:13 ` Paul Walmsley
0 siblings, 0 replies; 31+ messages in thread
From: Paul Walmsley @ 2014-07-15 20:13 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> > On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> >> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
> >>
> >> Cc: Tony Lindgren <tony@atomide.com>
> >> Cc: Russell King <linux@arm.linux.org.uk>
> >> Cc: Paul Walmsley <paul@pwsan.com>
> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> ---
> >> Changes from v1:
> >> * changed the clock domain to "pcie_clkdm"
> >> * Added PCIe as a slave port for l3_main.
> >
> > Looks good to me,
> > Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>
> Paul,
>
> Can you pick this one?
Yep, queued for 3.17.
- Paul
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
2014-07-15 20:13 ` Paul Walmsley
(?)
@ 2014-07-16 4:45 ` Kishon Vijay Abraham I
-1 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-16 4:45 UTC (permalink / raw)
To: Paul Walmsley
Cc: devicetree, linux-pci, linux-omap, tony, linux, linux-arm-kernel,
linux-kernel
On Wednesday 16 July 2014 01:43 AM, Paul Walmsley wrote:
> On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
>
>> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
>>> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>>>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>>>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>> Cc: Paul Walmsley <paul@pwsan.com>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> ---
>>>> Changes from v1:
>>>> * changed the clock domain to "pcie_clkdm"
>>>> * Added PCIe as a slave port for l3_main.
>>>
>>> Looks good to me,
>>> Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>>
>> Paul,
>>
>> Can you pick this one?
>
> Yep, queued for 3.17.
Thanks :-)
-Kishon
>
> - Paul
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-16 4:45 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-16 4:45 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 16 July 2014 01:43 AM, Paul Walmsley wrote:
> On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
>
>> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
>>> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>>>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>>>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>> Cc: Paul Walmsley <paul@pwsan.com>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> ---
>>>> Changes from v1:
>>>> * changed the clock domain to "pcie_clkdm"
>>>> * Added PCIe as a slave port for l3_main.
>>>
>>> Looks good to me,
>>> Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>>
>> Paul,
>>
>> Can you pick this one?
>
> Yep, queued for 3.17.
Thanks :-)
-Kishon
>
> - Paul
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v2] arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
@ 2014-07-16 4:45 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 31+ messages in thread
From: Kishon Vijay Abraham I @ 2014-07-16 4:45 UTC (permalink / raw)
To: Paul Walmsley
Cc: devicetree, linux-pci, linux-omap, tony, linux, linux-arm-kernel,
linux-kernel
On Wednesday 16 July 2014 01:43 AM, Paul Walmsley wrote:
> On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
>
>> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
>>> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>>>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>>>
>>>> Cc: Tony Lindgren <tony@atomide.com>
>>>> Cc: Russell King <linux@arm.linux.org.uk>
>>>> Cc: Paul Walmsley <paul@pwsan.com>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> ---
>>>> Changes from v1:
>>>> * changed the clock domain to "pcie_clkdm"
>>>> * Added PCIe as a slave port for l3_main.
>>>
>>> Looks good to me,
>>> Reviewed-by: Rajendra Nayak <rnayak@ti.com>
>>
>> Paul,
>>
>> Can you pick this one?
>
> Yep, queued for 3.17.
Thanks :-)
-Kishon
>
> - Paul
>
^ permalink raw reply [flat|nested] 31+ messages in thread