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From: Dave Hansen <dave@sr71.net>
To: Mel Gorman <mgorman@suse.de>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	akpm@linux-foundation.org, kirill.shutemov@linux.intel.com,
	ak@linux.intel.com, riel@redhat.com, alex.shi@linaro.org,
	dave.hansen@linux.intel.com, "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH 5/6] x86: mm: new tunable for single vs full TLB flush
Date: Mon, 07 Jul 2014 10:43:37 -0700	[thread overview]
Message-ID: <53BADC49.6000600@sr71.net> (raw)
In-Reply-To: <20140424103727.GT23991@suse.de>

On 04/24/2014 03:37 AM, Mel Gorman wrote:
>> +Despite the fact that a single individual flush on x86 is
>> > +guaranteed to flush a full 2MB, hugetlbfs always uses the full
>> > +flushes.  THP is treated exactly the same as normal memory.
>> > +
> You are the second person that told me this and I felt the manual was
> unclear on this subject. I was told that it might be a documentation bug
> but because this discussion was in a bar I completely failed to follow up
> on it. 

For the record...  There's a new version of the Intel SDM out, and it
contains some clarifications.  They're the easiest to find in this
document which highlights the deltas from the last version:

> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developers-manual.pdf

The documentation for invlpg itself has a new footnote, and there's also
a little bit of new text in section "4.10.2.3 Details of TLB Use".

The footnotes say:

	If the paging structures map the linear address using a page
	larger than 4 KBytes and there are multiple TLB entries for
	that page (see Section 4.10.2.3), the instruction (invlpg)
	invalidates all of them

I hope that clears up some of the ambiguity over invlpg.

--
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WARNING: multiple messages have this Message-ID (diff)
From: Dave Hansen <dave@sr71.net>
To: Mel Gorman <mgorman@suse.de>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	akpm@linux-foundation.org, kirill.shutemov@linux.intel.com,
	ak@linux.intel.com, riel@redhat.com, alex.shi@linaro.org,
	dave.hansen@linux.intel.com, "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH 5/6] x86: mm: new tunable for single vs full TLB flush
Date: Mon, 07 Jul 2014 10:43:37 -0700	[thread overview]
Message-ID: <53BADC49.6000600@sr71.net> (raw)
In-Reply-To: <20140424103727.GT23991@suse.de>

On 04/24/2014 03:37 AM, Mel Gorman wrote:
>> +Despite the fact that a single individual flush on x86 is
>> > +guaranteed to flush a full 2MB, hugetlbfs always uses the full
>> > +flushes.  THP is treated exactly the same as normal memory.
>> > +
> You are the second person that told me this and I felt the manual was
> unclear on this subject. I was told that it might be a documentation bug
> but because this discussion was in a bar I completely failed to follow up
> on it. 

For the record...  There's a new version of the Intel SDM out, and it
contains some clarifications.  They're the easiest to find in this
document which highlights the deltas from the last version:

> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developers-manual.pdf

The documentation for invlpg itself has a new footnote, and there's also
a little bit of new text in section "4.10.2.3 Details of TLB Use".

The footnotes say:

	If the paging structures map the linear address using a page
	larger than 4 KBytes and there are multiple TLB entries for
	that page (see Section 4.10.2.3), the instruction (invlpg)
	invalidates all of them

I hope that clears up some of the ambiguity over invlpg.

  parent reply	other threads:[~2014-07-07 17:43 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-21 18:24 [PATCH 0/6] x86: rework tlb range flushing code Dave Hansen
2014-04-21 18:24 ` Dave Hansen
2014-04-21 18:24 ` [PATCH 1/6] x86: mm: clean up tlb " Dave Hansen
2014-04-21 18:24   ` Dave Hansen
2014-04-22 16:53   ` Rik van Riel
2014-04-22 16:53     ` Rik van Riel
2014-04-24  8:33   ` Mel Gorman
2014-04-24  8:33     ` Mel Gorman
2014-04-21 18:24 ` [PATCH 2/6] x86: mm: rip out complicated, out-of-date, buggy TLB flushing Dave Hansen
2014-04-21 18:24   ` Dave Hansen
2014-04-22 16:54   ` Rik van Riel
2014-04-22 16:54     ` Rik van Riel
2014-04-24  8:45   ` Mel Gorman
2014-04-24  8:45     ` Mel Gorman
2014-04-24 16:58     ` Dave Hansen
2014-04-24 16:58       ` Dave Hansen
2014-04-24 18:00       ` Mel Gorman
2014-04-24 18:00         ` Mel Gorman
2014-04-25 21:39     ` Dave Hansen
2014-04-25 21:39       ` Dave Hansen
2014-04-21 18:24 ` [PATCH 3/6] x86: mm: fix missed global TLB flush stat Dave Hansen
2014-04-21 18:24   ` Dave Hansen
2014-04-22 17:15   ` Rik van Riel
2014-04-22 17:15     ` Rik van Riel
2014-04-24  8:49   ` Mel Gorman
2014-04-24  8:49     ` Mel Gorman
2014-04-21 18:24 ` [PATCH 4/6] x86: mm: trace tlb flushes Dave Hansen
2014-04-21 18:24   ` Dave Hansen
2014-04-22 21:19   ` Rik van Riel
2014-04-22 21:19     ` Rik van Riel
2014-04-24 10:14   ` Mel Gorman
2014-04-24 10:14     ` Mel Gorman
2014-04-24 20:42     ` Dave Hansen
2014-04-24 20:42       ` Dave Hansen
2014-04-21 18:24 ` [PATCH 5/6] x86: mm: new tunable for single vs full TLB flush Dave Hansen
2014-04-21 18:24   ` Dave Hansen
2014-04-22 21:31   ` Rik van Riel
2014-04-22 21:31     ` Rik van Riel
2014-04-24 10:37   ` Mel Gorman
2014-04-24 10:37     ` Mel Gorman
2014-04-24 17:25     ` Dave Hansen
2014-04-24 17:25       ` Dave Hansen
2014-04-24 17:53       ` Rik van Riel
2014-04-24 17:53         ` Rik van Riel
2014-04-24 22:03         ` Dave Hansen
2014-04-24 22:03           ` Dave Hansen
2014-07-07 17:43     ` Dave Hansen [this message]
2014-07-07 17:43       ` Dave Hansen
2014-07-08  0:43       ` Alex Shi
2014-07-08  0:43         ` Alex Shi
2014-04-21 18:24 ` [PATCH 6/6] x86: mm: set TLB flush tunable to sane value (33) Dave Hansen
2014-04-21 18:24   ` Dave Hansen
2014-04-22 21:33   ` Rik van Riel
2014-04-22 21:33     ` Rik van Riel
2014-04-24 10:46   ` Mel Gorman
2014-04-24 10:46     ` Mel Gorman

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