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From: Alexander Graf <agraf@suse.de>
To: Peter Maydell <peter.maydell@linaro.org>,
	Alexey Kardashevskiy <aik@ozlabs.ru>
Cc: Tom Musta <tommusta@gmail.com>,
	"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Greg Kurz <gkurz@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [PATCH v5 30/30] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE
Date: Tue, 08 Jul 2014 16:45:39 +0200	[thread overview]
Message-ID: <53BC0413.7060007@suse.de> (raw)
In-Reply-To: <CAFEAcA8CrW0i6nirGE3z9HfLtbLLpa9+cQViAEenByWvOJGyGg@mail.gmail.com>


On 08.07.14 16:37, Peter Maydell wrote:
> On 4 June 2014 13:51, Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
>> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
>> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>>
>> This defines AIL flags for LPCR special register.
>>
>> This changes @excp_prefix according to the mode, takes effect in TCG.
>>
>> This turns support of a new capability PPC2_ISA207S flag for TCG.
> I see this has hit master already, but:
>
>> +static target_ulong h_set_mode_resouce_addr_trans_mode(PowerPCCPU *cpu,
>> +                                                       target_ulong mflags,
>> +                                                       target_ulong value1,
>> +                                                       target_ulong value2)
>
> "resource" has two 'r's in it.
>
>> +{
>> +    CPUState *cs;
>> +    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
>> +    target_ulong prefix;
>> +
>> +    if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
>> +        return H_P2;
>> +    }
>> +    if (value1) {
>> +        return H_P3;
>> +    }
>> +    if (value2) {
>> +        return H_P4;
>> +    }
>> +
>> +    switch (mflags) {
>> +    case H_SET_MODE_ADDR_TRANS_NONE:
>> +        prefix = 0;
>> +        break;
>> +    case H_SET_MODE_ADDR_TRANS_0001_8000:
>> +        prefix = 0x18000;
>> +        break;
>> +    case H_SET_MODE_ADDR_TRANS_C000_0000_0000_4000:
>> +        prefix = 0xC000000000004000;
> Needs an ULL suffix to avoid warnings on 32 bit:
>
> /home/petmay01/linaro/qemu-from-laptop/qemu/hw/ppc/spapr_hcall.c: In
> function ‘h_set_mode_resouce_addr_trans_mode’:
> /home/petmay01/linaro/qemu-from-laptop/qemu/hw/ppc/spapr_hcall.c:773:
> warning: integer constant is too large for ‘long’ type

Wow, and there I thought I always catch those ;).

Can you please quickly fix those up and commit then straight to the 
tree? I don't think we'll have to do the usual commit dance for changes 
as trivial as this.


Alex

  reply	other threads:[~2014-07-08 14:45 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-04 12:50 [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 01/30] target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRs Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 02/30] target-ppc: Merge 970FX and 970MP into a single 970 class Alexey Kardashevskiy
2014-06-04 17:27   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 03/30] target-ppc: Refactor PPC970 Alexey Kardashevskiy
2014-06-04 17:27   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 04/30] target-ppc: Make UCTRL a mirror of CTRL Alexey Kardashevskiy
2014-06-04 17:27   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 05/30] target-ppc: Copy and split gen_spr_7xx() for 970 Alexey Kardashevskiy
2014-06-04 17:27   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 06/30] target-ppc: Add "POWER" prefix to MMCRA PMU registers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 07/30] target-ppc: Add PMC5/6, SDAR and MMCRA to 970 family Alexey Kardashevskiy
2014-06-04 17:28   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 08/30] target-ppc: Add PMC7/8 to 970 class Alexey Kardashevskiy
2014-06-04 17:28   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 09/30] target-ppc: Add HID4 SPR for PPC970 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 10/30] target-ppc: Introduce and reuse generalized init_proc_book3s_64() Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 11/30] target-ppc: Remove check_pow_970FX Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 12/30] target-ppc: Enable PMU SPRs migration Alexey Kardashevskiy
2014-06-04 17:28   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 13/30] target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 14/30] target-ppc: Move POWER8 TCE Address control (TAR) to a helper Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 15/30] target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpers Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 16/30] target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 17/30] target-ppc: Make use of gen_spr_power5p_lpar() " Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 18/30] target-ppc: Switch POWER7/8 classes to use correct PMU SPRs Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 19/30] target-ppc: Refactor class init for POWER7/8 Alexey Kardashevskiy
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 20/30] target-ppc: Add POWER8's TIR SPR Alexey Kardashevskiy
2014-06-04 17:29   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 21/30] target-ppc: Add POWER8's FSCR SPR Alexey Kardashevskiy
2014-06-04 17:29   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 22/30] target-ppc: Enable FSCR facility check for TAR Alexey Kardashevskiy
2014-06-04 17:29   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 23/30] target-ppc: Add POWER8's MMCR2/MMCRS SPRs Alexey Kardashevskiy
2014-06-04 17:29   ` Tom Musta
2014-06-04 12:50 ` [Qemu-devel] [PATCH v5 24/30] target-ppc: Add POWER8's TM SPRs Alexey Kardashevskiy
2014-06-04 17:30   ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 25/30] KVM: target-ppc: Enable TM state migration Alexey Kardashevskiy
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 26/30] target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs Alexey Kardashevskiy
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 27/30] target-ppc: Enable PPR and VRSAVE SPRs migration Alexey Kardashevskiy
2014-06-04 17:30   ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 28/30] target-ppc: Enable DABRX SPR and limit it to <=POWER7 Alexey Kardashevskiy
2014-06-04 17:30   ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 29/30] spapr_hcall: Split h_set_mode() Alexey Kardashevskiy
2014-06-04 17:30   ` Tom Musta
2014-06-04 12:51 ` [Qemu-devel] [PATCH v5 30/30] spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODE Alexey Kardashevskiy
2014-06-04 17:30   ` Tom Musta
2014-07-08 14:37   ` Peter Maydell
2014-07-08 14:45     ` Alexander Graf [this message]
2014-06-04 17:37 ` [Qemu-devel] [PATCH v5 00/30] book3s powerpc classes (970, power5, power7, power8) rework Tom Musta
2014-06-04 21:51   ` Alexander Graf
2014-06-04 23:37     ` Alexey Kardashevskiy

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