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From: Leon Alrae <leon.alrae@imgtec.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com,
	QEMU Developers <qemu-devel@nongnu.org>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH v2 2/9] softmmu: provide softmmu access type enum
Date: Tue, 8 Jul 2014 17:08:24 +0100	[thread overview]
Message-ID: <53BC1778.2030908@imgtec.com> (raw)
In-Reply-To: <CAFEAcA_+u0+iLKRyrtUSWXTS_AaNNq1ciM9bZOtiWbK3UrMYDw@mail.gmail.com>

Hi Peter,

On 08/07/2014 14:00, Peter Maydell wrote:
> On 8 July 2014 08:57, Leon Alrae <leon.alrae@imgtec.com> wrote:
>> New MIPS features depend on the access type and enum is more convenient than
>> using the numbers directly.
>>
> Mmm, I've thought for a while it would be better to have this
> be an enum, but never got round to it.
> 
>> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
>> ---
>>  include/exec/cpu-common.h |    6 ++++++
>>  softmmu_template.h        |   26 ++++++++++++++++----------
>>  2 files changed, 22 insertions(+), 10 deletions(-)
>>
>> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
>> index e3ec4c8..1c3171a 100644
>> --- a/include/exec/cpu-common.h
>> +++ b/include/exec/cpu-common.h
>> @@ -26,6 +26,12 @@ typedef struct CPUListState {
>>      FILE *file;
>>  } CPUListState;
>>
>> +enum mmu_access_type {
> 
> CODING_STYLE says enum names should be CamelCase.
> I think you also want this to be a typedef.

The style was copied from "enum device_endian {" which is few lines
below, I assumed it was correct :) I'll fix this.

>> +    MMU_DATA_LOAD  = 0,
>> +    MMU_DATA_STORE = 1,
>> +    MMU_INST_FETCH = 2
>> +};
>> +
> 
> We should probably also chase through and update the
> prototypes of functions like tlb_fill() and cpu_unaligned_access()
> and so on to take this enum type rather than int. (I
> suspect there's a lot of those running into different
> targets so it might need doing over multiple patches.)
> 
> thanks
> -- PMM
> 

I intentionally skipped this here to focus this patchset on the new
features only. I also think that eventually we will have to update the
prototypes and go through all the targets.

Thanks,
Leon

  reply	other threads:[~2014-07-08 16:08 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-08  7:57 [Qemu-devel] [PATCH v2 0/9] target-mips: implement features required in MIPS64 Release 6 Leon Alrae
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers Leon Alrae
2014-10-14 13:59   ` Yongbok Kim
2014-10-20 12:54     ` Leon Alrae
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 2/9] softmmu: provide softmmu access type enum Leon Alrae
2014-07-08 13:00   ` Peter Maydell
2014-07-08 16:08     ` Leon Alrae [this message]
2014-07-08 16:12       ` Peter Maydell
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 3/9] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-10-14 15:55   ` Yongbok Kim
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 4/9] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-10-15 12:24   ` Yongbok Kim
2014-10-24 14:16     ` Leon Alrae
2014-10-24 14:27       ` Yongbok Kim
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 5/9] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-10-15 15:20   ` Yongbok Kim
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 6/9] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-10-15 15:39   ` Yongbok Kim
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 7/9] target-mips: add TLBINV support Leon Alrae
2014-10-16 10:52   ` Yongbok Kim
2014-10-16 13:03     ` Leon Alrae
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 8/9] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-07-08 12:44   ` James Hogan
2014-07-08 15:56     ` Leon Alrae
2014-07-08  7:57 ` [Qemu-devel] [PATCH v2 9/9] target-mips: update cpu_save/cpu_load to support new registers Leon Alrae
2014-10-16 13:06   ` Yongbok Kim

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