From: Leon Alrae <leon.alrae@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers
Date: Mon, 20 Oct 2014 13:54:11 +0100 [thread overview]
Message-ID: <544505F3.1010207@imgtec.com> (raw)
In-Reply-To: <543D2C4F.8040308@imgtec.com>
Hi Yongbok,
On 14/10/2014 14:59, Yongbok Kim wrote:
>> @@ -4611,6 +4612,15 @@ static inline void gen_mtc0_store64 (TCGv arg,
>> target_ulong off)
>> tcg_gen_st_tl(arg, cpu_env, off);
>> }
>> +static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
>> +{
>> + if (ctx->insn_flags & ISA_MIPS32R6) {
>> + tcg_gen_movi_tl(arg, 0);
>> + } else {
>> + tcg_gen_movi_tl(arg, ~0);
>> + }
>> +}
>> +
>
> Not related with KScratch registers. It would be better to be a separate
> patch or
> as part of the patch [PATCH 5/6] target-mips: correctly handle access to
> unimplemented CP0 register.
Actually it is related to all cp0 registers and KScratch is the first
cp0 register added in the series, thus in my opinion this is a good
place for including the definition of gen_mfc0_unimplemented(). The
patch you mentioned is correcting the remaining (existing before this
patch) cp0 registers.
Regards,
Leon
next prev parent reply other threads:[~2014-10-20 12:54 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-08 7:57 [Qemu-devel] [PATCH v2 0/9] target-mips: implement features required in MIPS64 Release 6 Leon Alrae
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 1/9] target-mips: add KScratch registers Leon Alrae
2014-10-14 13:59 ` Yongbok Kim
2014-10-20 12:54 ` Leon Alrae [this message]
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 2/9] softmmu: provide softmmu access type enum Leon Alrae
2014-07-08 13:00 ` Peter Maydell
2014-07-08 16:08 ` Leon Alrae
2014-07-08 16:12 ` Peter Maydell
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 3/9] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-10-14 15:55 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 4/9] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-10-15 12:24 ` Yongbok Kim
2014-10-24 14:16 ` Leon Alrae
2014-10-24 14:27 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 5/9] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-10-15 15:20 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 6/9] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-10-15 15:39 ` Yongbok Kim
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 7/9] target-mips: add TLBINV support Leon Alrae
2014-10-16 10:52 ` Yongbok Kim
2014-10-16 13:03 ` Leon Alrae
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 8/9] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-07-08 12:44 ` James Hogan
2014-07-08 15:56 ` Leon Alrae
2014-07-08 7:57 ` [Qemu-devel] [PATCH v2 9/9] target-mips: update cpu_save/cpu_load to support new registers Leon Alrae
2014-10-16 13:06 ` Yongbok Kim
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