[patch] perf_event_open.2 -- clarify PERF_SAMPLE_DATA_SRC usage

[patch] perf_event_open.2 -- clarify PERF_SAMPLE_DATA_SRC usage

[Vince Weaver]

When checking the fields in the PERF_SAMPLE_DATA_SRC type samples you need 
to shift the masks before doing the compare.

Although the value you are checking (perf_mem_data_src) is specified as a 
bitfield so this might all far apart if trying to access the field in a 
cross-endian way.  The Power people were working on this issue, not sure
if they resolved it.

Signed-off-by: Vince Weaver <vincent.weaver-e7X0jjDqjFGHXe+LvDLADg@public.gmane.org>

diff --git a/man2/perf_event_open.2 b/man2/perf_event_open.2
index 47e9984..3d70300 100644
--- a/man2/perf_event_open.2
+++ b/man2/perf_event_open.2
@@ -1935,7 +1935,9 @@ Executable code
 .PD
 .TP
 .I mem_lvl
-Memory hierarchy level hit or miss, a bitwise combination of:
+Memory hierarchy level hit or miss, a bitwise combination of
+the following, shifted left by 
+.BR PERF_MEM_LVL_SHIFT :
 
 .PD 0
 .RS
@@ -1985,7 +1987,8 @@ Uncached memory
 .PD
 .TP
 .I mem_snoop
-Snoop mode, a bitwise combination of:
+Snoop mode, a bitwise combination of the following, shifted left by
+.BR PERF_MEM_SNOOP_SHIFT :
 
 .PD 0
 .RS
@@ -2008,7 +2011,8 @@ Snoop hit modified
 .PD
 .TP
 .I mem_lock
-Lock instruction, a bitwise combination of:
+Lock instruction, a bitwise combination of the following, shifted left by
+.BR PERF_MEM_LOCK_SHIFT :
 
 .PD 0
 .RS
@@ -2022,7 +2026,9 @@ Locked transaction
 .PD
 .TP
 .I mem_dtlb
-TLB access hit or miss, a bitwise combination of:
+TLB access hit or miss, a bitwise combination of the following, shifted
+left by
+.BR PERF_MEM_TLB_SHIFT :
 
 .PD 0
 .RS
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Re: [patch] perf_event_open.2 -- clarify PERF_SAMPLE_DATA_SRC usage

[Michael Kerrisk (man-pages)]

On 07/14/2014 04:33 PM, Vince Weaver wrote:
> 
> When checking the fields in the PERF_SAMPLE_DATA_SRC type samples you need 
> to shift the masks before doing the compare.
> 
> Although the value you are checking (perf_mem_data_src) is specified as a 
> bitfield so this might all far apart if trying to access the field in a 
> cross-endian way.  The Power people were working on this issue, not sure
> if they resolved it.

Thanks, Vince. Applied.

In the changelog text above, I changed "far" to "fall". Okay?

Cheers,

Michael


> Signed-off-by: Vince Weaver <vincent.weaver-e7X0jjDqjFGHXe+LvDLADg@public.gmane.org>
> 
> diff --git a/man2/perf_event_open.2 b/man2/perf_event_open.2
> index 47e9984..3d70300 100644
> --- a/man2/perf_event_open.2
> +++ b/man2/perf_event_open.2
> @@ -1935,7 +1935,9 @@ Executable code
>  .PD
>  .TP
>  .I mem_lvl
> -Memory hierarchy level hit or miss, a bitwise combination of:
> +Memory hierarchy level hit or miss, a bitwise combination of
> +the following, shifted left by 
> +.BR PERF_MEM_LVL_SHIFT :
>  
>  .PD 0
>  .RS
> @@ -1985,7 +1987,8 @@ Uncached memory
>  .PD
>  .TP
>  .I mem_snoop
> -Snoop mode, a bitwise combination of:
> +Snoop mode, a bitwise combination of the following, shifted left by
> +.BR PERF_MEM_SNOOP_SHIFT :
>  
>  .PD 0
>  .RS
> @@ -2008,7 +2011,8 @@ Snoop hit modified
>  .PD
>  .TP
>  .I mem_lock
> -Lock instruction, a bitwise combination of:
> +Lock instruction, a bitwise combination of the following, shifted left by
> +.BR PERF_MEM_LOCK_SHIFT :
>  
>  .PD 0
>  .RS
> @@ -2022,7 +2026,9 @@ Locked transaction
>  .PD
>  .TP
>  .I mem_dtlb
> -TLB access hit or miss, a bitwise combination of:
> +TLB access hit or miss, a bitwise combination of the following, shifted
> +left by
> +.BR PERF_MEM_TLB_SHIFT :
>  
>  .PD 0
>  .RS
> 


-- 
Michael Kerrisk
Linux man-pages maintainer; http://www.kernel.org/doc/man-pages/
Linux/UNIX System Programming Training: http://man7.org/training/
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Re: [patch] perf_event_open.2 -- clarify PERF_SAMPLE_DATA_SRC usage

[Vince Weaver]

On Tue, 15 Jul 2014, Michael Kerrisk (man-pages) wrote:

> Thanks, Vince. Applied.
> 
> In the changelog text above, I changed "far" to "fall". Okay?

yes, that's fine.  I should obviously proofread the changelogs better 
before sending things off.

Vince
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