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From: Murali Karicheri <m-karicheri2@ti.com>
To: Rob Herring <robherring2@gmail.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Russell King <linux@arm.linux.org.uk>,
	Grant Likely <grant.likely@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Mohit Kumar <mohit.kumar@st.com>,
	Jingoo Han <jg1.han@samsung.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Pratyush Anand <pratyush.anand@st.com>,
	Richard Zhu <r65037@freescale.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Marek Vasut <marex@denx.de>, Arnd Bergmann <arnd@arndb.de>,
	Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	Randy Dunlap <rdunlap@infradead.org>
Subject: Re: [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w
Date: Fri, 18 Jul 2014 16:29:16 -0400	[thread overview]
Message-ID: <53C9839C.5090604@ti.com> (raw)
In-Reply-To: <CAL_JsqKheoWrSGtxPO=AE8g9iOAqfwRa=81Ku=Cfx8_gpDysOg@mail.gmail.com>

Rob,

On 07/18/2014 03:31 PM, Rob Herring wrote:
> On Fri, Jul 18, 2014 at 10:14 AM, Murali Karicheri<m-karicheri2@ti.com>  wrote:
--- Cut ---
>> +
>> +Optional properties:-
>> +       phys: phandle to Generic Keystone SerDes phy for PCI
>> +       phy-names: name of the Generic Keystine SerDes phy for PCI
>> +         - If boot loader already does PCI link establishment, then phys and
>> +           phy-names shouldn't be present.
>> +       ti,enable-linktrain - Enable Link training.
>> +         - If boot loader already does PCI link establishment, then this
>> +           shouldn't be present.
>
> Can't you read from the h/w if the link is trained?

Yes.

There are customers who use this driver with PCI Link setup done in the 
boot loader. This property tells the driver to bypass Link setup 
procedure in that case. Is this undesirable and if so. how other 
platforms handle it? Check first if link is trained or start the link 
setup procedure? Let me know. If this is fine, please provide your Ack.

Thanks.

Murali
>
> Rob


WARNING: multiple messages have this Message-ID (diff)
From: m-karicheri2@ti.com (Murali Karicheri)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w
Date: Fri, 18 Jul 2014 16:29:16 -0400	[thread overview]
Message-ID: <53C9839C.5090604@ti.com> (raw)
In-Reply-To: <CAL_JsqKheoWrSGtxPO=AE8g9iOAqfwRa=81Ku=Cfx8_gpDysOg@mail.gmail.com>

Rob,

On 07/18/2014 03:31 PM, Rob Herring wrote:
> On Fri, Jul 18, 2014 at 10:14 AM, Murali Karicheri<m-karicheri2@ti.com>  wrote:
--- Cut ---
>> +
>> +Optional properties:-
>> +       phys: phandle to Generic Keystone SerDes phy for PCI
>> +       phy-names: name of the Generic Keystine SerDes phy for PCI
>> +         - If boot loader already does PCI link establishment, then phys and
>> +           phy-names shouldn't be present.
>> +       ti,enable-linktrain - Enable Link training.
>> +         - If boot loader already does PCI link establishment, then this
>> +           shouldn't be present.
>
> Can't you read from the h/w if the link is trained?

Yes.

There are customers who use this driver with PCI Link setup done in the 
boot loader. This property tells the driver to bypass Link setup 
procedure in that case. Is this undesirable and if so. how other 
platforms handle it? Check first if link is trained or start the link 
setup procedure? Let me know. If this is fine, please provide your Ack.

Thanks.

Murali
>
> Rob

  parent reply	other threads:[~2014-07-18 20:30 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-18 15:14 [PATCH v6 0/5] Add Keystone PCIe controller driver Murali Karicheri
2014-07-18 15:14 ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 1/5] PCI: designware: add rd[wr]_other_conf API Murali Karicheri
2014-07-18 15:14   ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 2/5] PCI: designware: refactor MSI code to work with v3.65 dw hardware Murali Karicheri
2014-07-18 15:14   ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 3/5] PCI: designware: enhance dw_pcie_host_init() to support v3.65 DW hardware Murali Karicheri
2014-07-18 15:14   ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w Murali Karicheri
2014-07-18 15:14   ` Murali Karicheri
2014-07-18 19:31   ` Rob Herring
2014-07-18 19:31     ` Rob Herring
2014-07-18 19:50     ` Arnd Bergmann
2014-07-18 19:50       ` Arnd Bergmann
2014-07-18 20:15       ` Murali Karicheri
2014-07-18 20:15         ` Murali Karicheri
2014-07-22 15:37       ` Rob Herring
2014-07-22 15:37         ` Rob Herring
2014-07-22 19:00         ` Murali Karicheri
2014-07-22 19:00           ` Murali Karicheri
2014-07-18 20:29     ` Murali Karicheri [this message]
2014-07-18 20:29       ` Murali Karicheri
2014-07-21  1:44       ` Jingoo Han
2014-07-21  1:44         ` Jingoo Han
2014-07-21 16:39         ` Murali Karicheri
2014-07-21 16:39           ` Murali Karicheri
2014-07-22 15:41           ` Rob Herring
2014-07-22 15:41             ` Rob Herring
2014-07-22 18:58             ` Murali Karicheri
2014-07-22 18:58               ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 5/5] PCI: keystone: Update maintainer information Murali Karicheri
2014-07-18 15:14   ` Murali Karicheri
2014-07-18 15:19 ` [PATCH v6 0/5] Add Keystone PCIe controller driver Murali Karicheri

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