About erasure code optimizations for ARM

About erasure code optimizations for ARM

[Loic Dachary]

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Hi,

When using the jerasure plugin for erasure coded placement groups, it takes advantage of http://en.wikipedia.org/wiki/SIMD when running on an Intel processor. It would be nice to also use http://en.wikipedia.org/wiki/NEON_%28instruction_set%29 when running on an ARM processor.

The optimizations themselves are in the https://bitbucket.org/jimplank/gf-complete library. At compile time Ceph creates different flavors of the plugin ( https://github.com/ceph/ceph/blob/firefly/src/erasure-code/jerasure/Makefile.am#L73 ) depending on the capabilities of the compiler to generate the appropriate instructions for SIMD. At runtime Ceph selects the plugin ( https://github.com/ceph/ceph/blob/firefly/src/erasure-code/jerasure/ErasureCodePluginSelectJerasure.cc#L41 ) depending on the CPU capabilities ( https://github.com/ceph/ceph/blob/firefly/src/arch/intel.c#L55 ). 

NEON detection already exists in Ceph ( https://github.com/ceph/ceph/blob/firefly/src/arch/neon.c#L41 ) and adding more would be trivial.

A (very) naive approach would be to add #ifdef NEON in places such as https://bitbucket.org/jimplank/gf-complete/src/c25310f215bc97a37944339d331b000ba806d505/src/gf_w4.c?at=master#cl-492 when and if a function such as https://bitbucket.org/jimplank/gf-complete/src/c25310f215bc97a37944339d331b000ba806d505/src/gf_w4.c?at=master#cl-922 can be implemented with NEON instructions instead of SIMD.

Maybe it is more complex and it needs some kind of rearchitecture ?

Cheers
-- 
Loïc Dachary, Artisan Logiciel Libre


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