[patch] x86/pmc_atom: silence shift wrapping warnings in pmc_sleep_tmr_show()

[patch] x86/pmc_atom: silence shift wrapping warnings in pmc_sleep_tmr_show()

[Dan Carpenter]

I don't know if we really need 64 bits here but these variables are
declared as u64 and it can't hurt to cast this so we prevent any shift
wrapping.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>

diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 0d92ef6..0c424a6 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -174,11 +174,11 @@ static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
 	struct pmc_dev *pmc = s->private;
 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
 
-	s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
-	s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
-	s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
-	s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
-	s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
+	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
+	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
+	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
+	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
+	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
 
 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);

Re: [patch] x86/pmc_atom: silence shift wrapping warnings in pmc_sleep_tmr_show()

[Li, Aubrey]

On 2014/8/2 0:42, Kasagar, Srinidhi wrote:
> On Fri, Aug 01, 2014 at 11:27:15AM +0300, Dan Carpenter wrote:
>> I don't know if we really need 64 bits here but these variables are
>> declared as u64 and it can't hurt to cast this so we prevent any shift
>> wrapping.
> 
> Hmm..not sure the usage of u64 for these registers. AFAIK these registers
> are 32-bit wide..

I didn't declare the registers, I declared the variables in microsecond.

> 
> Aubrey, any reason declaring them as u64?

These registers are the time spent in units of 32us. So yes, we need
64bits here for the conversion.

> 
> Srinidhi
> 
>>
>> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>

The patch looks good to me.

Acked-by: Aubrey Li <aubrey.li@linux.intel.com>

>>
>> diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
>> index 0d92ef6..0c424a6 100644
>> --- a/arch/x86/kernel/pmc_atom.c
>> +++ b/arch/x86/kernel/pmc_atom.c
>> @@ -174,11 +174,11 @@ static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
>>  	struct pmc_dev *pmc = s->private;
>>  	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
>>  
>> -	s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
>> -	s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
>> -	s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
>> -	s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
>> -	s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
>> +	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
>> +	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
>> +	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
>> +	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
>> +	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
>>  
>>  	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
>>  	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
> 

[tip:x86/platform] x86/pmc_atom: Silence shift wrapping warnings in pmc_sleep_tmr_show()

[tip-bot for Dan Carpenter]

Commit-ID:  4c51cb005b29e6329d7e598bf835689b230817c9
Gitweb:     http://git.kernel.org/tip/4c51cb005b29e6329d7e598bf835689b230817c9
Author:     Dan Carpenter <dan.carpenter@oracle.com>
AuthorDate: Fri, 1 Aug 2014 11:27:15 +0300
Committer:  H. Peter Anvin <hpa@zytor.com>
CommitDate: Sat, 2 Aug 2014 16:52:17 -0700

x86/pmc_atom: Silence shift wrapping warnings in pmc_sleep_tmr_show()

I don't know if we really need 64 bits here but these variables are
declared as u64 and it can't hurt to cast this so we prevent any shift
wrapping.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Aubrey Li <aubrey.li@linux.intel.com>
Link: http://lkml.kernel.org/r/20140801082715.GE28869@mwanda
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
---
 arch/x86/kernel/pmc_atom.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 0d92ef6..0c424a6 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -174,11 +174,11 @@ static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
 	struct pmc_dev *pmc = s->private;
 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
 
-	s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
-	s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
-	s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
-	s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
-	s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
+	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
+	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
+	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
+	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
+	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
 
 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);