* [PATCH v3 1/3] of: Add NVIDIA Tegra flow controller bindings @ 2014-08-26 6:14 ` Thierry Reding 0 siblings, 0 replies; 8+ messages in thread From: Thierry Reding @ 2014-08-26 6:14 UTC (permalink / raw) To: Stephen Warren Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Add device tree bindings for the flow controller found on NVIDIA Tegra SoCs. Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- Changes in v3: - collapse identical bindings into a single file .../bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt new file mode 100644 index 000000000000..ccf0adddc820 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra Flow Controller + +Required properties: +- compatible: Should be "nvidia,tegra<chip>-flowctrl" +- reg: Should contain one register range (address and length) + +Example: + + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; -- 2.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 1/3] of: Add NVIDIA Tegra flow controller bindings @ 2014-08-26 6:14 ` Thierry Reding 0 siblings, 0 replies; 8+ messages in thread From: Thierry Reding @ 2014-08-26 6:14 UTC (permalink / raw) To: linux-arm-kernel From: Thierry Reding <treding@nvidia.com> Add device tree bindings for the flow controller found on NVIDIA Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v3: - collapse identical bindings into a single file .../bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt new file mode 100644 index 000000000000..ccf0adddc820 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt @@ -0,0 +1,12 @@ +NVIDIA Tegra Flow Controller + +Required properties: +- compatible: Should be "nvidia,tegra<chip>-flowctrl" +- reg: Should contain one register range (address and length) + +Example: + + flow-controller at 60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; -- 2.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
[parent not found: <1409033644-24376-1-git-send-email-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH v3 2/3] ARM: tegra: Add device tree nodes for flow controller 2014-08-26 6:14 ` Thierry Reding @ 2014-08-26 6:14 ` Thierry Reding -1 siblings, 0 replies; 8+ messages in thread From: Thierry Reding @ 2014-08-26 6:14 UTC (permalink / raw) To: Stephen Warren Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it. Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- arch/arm/boot/dts/tegra114.dtsi | 5 +++++ arch/arm/boot/dts/tegra124.dtsi | 5 +++++ arch/arm/boot/dts/tegra20.dtsi | 5 +++++ arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 08442d9abec7..430f85ac27f6 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -161,6 +161,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a2e3e25fe736..5d1b32225dc2 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -210,6 +210,11 @@ #reset-cells = <1>; }; + flow-controller@0,60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index e44cb596c589..c6a2d078bdf4 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -201,6 +201,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c0136bf2c5da..f4693c9c070e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -282,6 +282,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; -- 2.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/3] ARM: tegra: Add device tree nodes for flow controller @ 2014-08-26 6:14 ` Thierry Reding 0 siblings, 0 replies; 8+ messages in thread From: Thierry Reding @ 2014-08-26 6:14 UTC (permalink / raw) To: linux-arm-kernel From: Thierry Reding <treding@nvidia.com> These nodes are required so that the flow controller driver can obtain the I/O memory region from device tree rather than hard-coding it. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> --- arch/arm/boot/dts/tegra114.dtsi | 5 +++++ arch/arm/boot/dts/tegra124.dtsi | 5 +++++ arch/arm/boot/dts/tegra20.dtsi | 5 +++++ arch/arm/boot/dts/tegra30.dtsi | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 08442d9abec7..430f85ac27f6 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -161,6 +161,11 @@ #reset-cells = <1>; }; + flow-controller at 60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma at 6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a2e3e25fe736..5d1b32225dc2 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -210,6 +210,11 @@ #reset-cells = <1>; }; + flow-controller at 0,60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + gpio: gpio at 0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index e44cb596c589..c6a2d078bdf4 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -201,6 +201,11 @@ #reset-cells = <1>; }; + flow-controller at 60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma at 6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c0136bf2c5da..f4693c9c070e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -282,6 +282,11 @@ #reset-cells = <1>; }; + flow-controller at 60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma at 6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; -- 2.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/3] ARM: tegra: Initialize flow controller from DT 2014-08-26 6:14 ` Thierry Reding @ 2014-08-26 6:14 ` Thierry Reding -1 siblings, 0 replies; 8+ messages in thread From: Thierry Reding @ 2014-08-26 6:14 UTC (permalink / raw) To: Stephen Warren Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Use a matching device tree node to initialize the flow controller driver instead of hard-coding the I/O address. This is necessary to get rid of the iomap.h include, which in turn make it easier to share this code with 64-bit Tegra SoCs. Acked-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Signed-off-by: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> --- Changes in v2: - implement fallback when the device tree node is missing - while at it, reorder includes alphabetically arch/arm/mach-tegra/flowctrl.c | 44 +++++++++++++++++++++++++++++++++++------- arch/arm/mach-tegra/flowctrl.h | 2 ++ arch/arm/mach-tegra/tegra.c | 2 ++ 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index ec55d1de1b55..475e783992fd 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -22,11 +22,12 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <soc/tegra/fuse.h> #include "flowctrl.h" -#include "iomap.h" static u8 flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, @@ -42,23 +43,22 @@ static u8 flowctrl_offset_cpu_csr[] = { FLOW_CTRL_CPU1_CSR + 16, }; +static void __iomem *tegra_flowctrl_base; + static void flowctrl_update(u8 offset, u32 value) { - void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; - - writel(value, addr); + writel(value, tegra_flowctrl_base + offset); /* ensure the update has reached the flow controller */ wmb(); - readl_relaxed(addr); + readl_relaxed(tegra_flowctrl_base + offset); } u32 flowctrl_read_cpu_csr(unsigned int cpuid) { u8 offset = flowctrl_offset_cpu_csr[cpuid]; - void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; - return readl(addr); + return readl(tegra_flowctrl_base + offset); } void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) @@ -139,3 +139,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ flowctrl_write_cpu_csr(cpuid, reg); } + +static const struct of_device_id matches[] __initconst = { + { .compatible = "nvidia,tegra124-flowctrl" }, + { .compatible = "nvidia,tegra114-flowctrl" }, + { .compatible = "nvidia,tegra30-flowctrl" }, + { .compatible = "nvidia,tegra20-flowctrl" }, + { } +}; + +void __init tegra_flowctrl_init(void) +{ + /* hardcoded fallback if device tree node is missing */ + unsigned long base = 0x60007000; + unsigned long size = SZ_4K; + struct device_node *np; + + np = of_find_matching_node(NULL, matches); + if (np) { + struct resource res; + + if (of_address_to_resource(np, 0, &res) == 0) { + size = resource_size(&res); + base = res.start; + } + + of_node_put(np); + } + + tegra_flowctrl_base = ioremap_nocache(base, size); +} diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index c89aac60a143..73a9c5016c1a 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); void flowctrl_cpu_suspend_enter(unsigned int cpuid); void flowctrl_cpu_suspend_exit(unsigned int cpuid); + +void tegra_flowctrl_init(void); #endif #endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 5ef5173dec83..ef016af1c9e7 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -48,6 +48,7 @@ #include "board.h" #include "common.h" #include "cpuidle.h" +#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" @@ -74,6 +75,7 @@ static void __init tegra_init_early(void) { of_register_trusted_foundations(); tegra_cpu_reset_handler_init(); + tegra_flowctrl_init(); } static void __init tegra_dt_init_irq(void) -- 2.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 3/3] ARM: tegra: Initialize flow controller from DT @ 2014-08-26 6:14 ` Thierry Reding 0 siblings, 0 replies; 8+ messages in thread From: Thierry Reding @ 2014-08-26 6:14 UTC (permalink / raw) To: linux-arm-kernel From: Thierry Reding <treding@nvidia.com> Use a matching device tree node to initialize the flow controller driver instead of hard-coding the I/O address. This is necessary to get rid of the iomap.h include, which in turn make it easier to share this code with 64-bit Tegra SoCs. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> --- Changes in v2: - implement fallback when the device tree node is missing - while at it, reorder includes alphabetically arch/arm/mach-tegra/flowctrl.c | 44 +++++++++++++++++++++++++++++++++++------- arch/arm/mach-tegra/flowctrl.h | 2 ++ arch/arm/mach-tegra/tegra.c | 2 ++ 3 files changed, 41 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index ec55d1de1b55..475e783992fd 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -22,11 +22,12 @@ #include <linux/init.h> #include <linux/io.h> #include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_address.h> #include <soc/tegra/fuse.h> #include "flowctrl.h" -#include "iomap.h" static u8 flowctrl_offset_halt_cpu[] = { FLOW_CTRL_HALT_CPU0_EVENTS, @@ -42,23 +43,22 @@ static u8 flowctrl_offset_cpu_csr[] = { FLOW_CTRL_CPU1_CSR + 16, }; +static void __iomem *tegra_flowctrl_base; + static void flowctrl_update(u8 offset, u32 value) { - void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; - - writel(value, addr); + writel(value, tegra_flowctrl_base + offset); /* ensure the update has reached the flow controller */ wmb(); - readl_relaxed(addr); + readl_relaxed(tegra_flowctrl_base + offset); } u32 flowctrl_read_cpu_csr(unsigned int cpuid) { u8 offset = flowctrl_offset_cpu_csr[cpuid]; - void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset; - return readl(addr); + return readl(tegra_flowctrl_base + offset); } void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) @@ -139,3 +139,33 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */ flowctrl_write_cpu_csr(cpuid, reg); } + +static const struct of_device_id matches[] __initconst = { + { .compatible = "nvidia,tegra124-flowctrl" }, + { .compatible = "nvidia,tegra114-flowctrl" }, + { .compatible = "nvidia,tegra30-flowctrl" }, + { .compatible = "nvidia,tegra20-flowctrl" }, + { } +}; + +void __init tegra_flowctrl_init(void) +{ + /* hardcoded fallback if device tree node is missing */ + unsigned long base = 0x60007000; + unsigned long size = SZ_4K; + struct device_node *np; + + np = of_find_matching_node(NULL, matches); + if (np) { + struct resource res; + + if (of_address_to_resource(np, 0, &res) == 0) { + size = resource_size(&res); + base = res.start; + } + + of_node_put(np); + } + + tegra_flowctrl_base = ioremap_nocache(base, size); +} diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h index c89aac60a143..73a9c5016c1a 100644 --- a/arch/arm/mach-tegra/flowctrl.h +++ b/arch/arm/mach-tegra/flowctrl.h @@ -59,6 +59,8 @@ void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); void flowctrl_cpu_suspend_enter(unsigned int cpuid); void flowctrl_cpu_suspend_exit(unsigned int cpuid); + +void tegra_flowctrl_init(void); #endif #endif diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 5ef5173dec83..ef016af1c9e7 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c @@ -48,6 +48,7 @@ #include "board.h" #include "common.h" #include "cpuidle.h" +#include "flowctrl.h" #include "iomap.h" #include "irq.h" #include "pm.h" @@ -74,6 +75,7 @@ static void __init tegra_init_early(void) { of_register_trusted_foundations(); tegra_cpu_reset_handler_init(); + tegra_flowctrl_init(); } static void __init tegra_dt_init_irq(void) -- 2.0.4 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/3] of: Add NVIDIA Tegra flow controller bindings 2014-08-26 6:14 ` Thierry Reding @ 2014-08-26 17:49 ` Stephen Warren -1 siblings, 0 replies; 8+ messages in thread From: Stephen Warren @ 2014-08-26 17:49 UTC (permalink / raw) To: Thierry Reding Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA On 08/26/2014 12:14 AM, Thierry Reding wrote: > From: Thierry Reding <treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > > Add device tree bindings for the flow controller found on NVIDIA Tegra > SoCs. I have applied patches 1,3 to Tegra's for-3.18/soc branch, and patch 2 to Tegra's for-3.18/dt branch. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/3] of: Add NVIDIA Tegra flow controller bindings @ 2014-08-26 17:49 ` Stephen Warren 0 siblings, 0 replies; 8+ messages in thread From: Stephen Warren @ 2014-08-26 17:49 UTC (permalink / raw) To: linux-arm-kernel On 08/26/2014 12:14 AM, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > Add device tree bindings for the flow controller found on NVIDIA Tegra > SoCs. I have applied patches 1,3 to Tegra's for-3.18/soc branch, and patch 2 to Tegra's for-3.18/dt branch. ^ permalink raw reply [flat|nested] 8+ messages in thread
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2014-08-26 6:14 ` [PATCH v3 2/3] ARM: tegra: Add device tree nodes for flow controller Thierry Reding
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2014-08-26 6:14 ` [PATCH v3 3/3] ARM: tegra: Initialize flow controller from DT Thierry Reding
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2014-08-26 17:49 ` [PATCH v3 1/3] of: Add NVIDIA Tegra flow controller bindings Stephen Warren
2014-08-26 17:49 ` Stephen Warren
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