diff for duplicates of <53FF17A0.1030100@samsung.com> diff --git a/a/1.txt b/N1/1.txt index 61cbf67..e9b20c0 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -32,44 +32,3 @@ http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=8132/1 > > Will > - --------------- next part -------------- -ARM: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSET - -From: Konstantin Khlebnikov <k.khlebnikov@samsung.com> - -In commit 7fb00c2fca4b6c58be521eb3676cf4b4ba8dde3b ("ARM: 8114/1: LPAE: -load upper bits of early TTBR0/TTBR1") part which fixes carrying in adding -TTBR1_OFFSET to TTRR1 was wrong: - - addls \ttbr1, \ttbr1, #TTBR1_OFFSET - adcls \tmp, \tmp, #0 - -addls doesn't update flags, adcls adds carry from cmp above: - - cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? - -Condition 'ls' means carry flag is clear or zero flag is set, thus only one -case is affected: when PHYS_OFFSET == PAGE_OFFSET. - -It seems safer to remove this fixup. Bug is here for ages and nobody -complained. Let's fix it separately. - -Signed-off-by: Konstantin Khlebnikov <k.khlebnikov@samsung.com> -Reported-and-tested-by: Jassi Brar <jassisinghbrar@gmail.com> ---- - arch/arm/mm/proc-v7-3level.S | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S -index 1a24e92..b64e67c 100644 ---- a/arch/arm/mm/proc-v7-3level.S -+++ b/arch/arm/mm/proc-v7-3level.S -@@ -146,7 +146,6 @@ ENDPROC(cpu_v7_set_pte_ext) - mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits - mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits - addls \ttbr1, \ttbr1, #TTBR1_OFFSET -- adcls \tmp, \tmp, #0 - mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1 - mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits - mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..03be9f6 --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,6 @@ +Content-Type: text/plain; charset=UTF-8; + name="arm-lpae-remove-carry-flag-correction-after-adding-ttbr1_offset" +Content-Transfer-Encoding: 7bit +Content-Disposition: attachment; + filename*0="arm-lpae-remove-carry-flag-correction-after-adding-ttbr1_off"; + filename*1="set" diff --git a/N1/2.txt b/N1/2.txt new file mode 100644 index 0000000..55ea407 --- /dev/null +++ b/N1/2.txt @@ -0,0 +1,39 @@ +ARM: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSET + +From: Konstantin Khlebnikov <k.khlebnikov@samsung.com> + +In commit 7fb00c2fca4b6c58be521eb3676cf4b4ba8dde3b ("ARM: 8114/1: LPAE: +load upper bits of early TTBR0/TTBR1") part which fixes carrying in adding +TTBR1_OFFSET to TTRR1 was wrong: + + addls \ttbr1, \ttbr1, #TTBR1_OFFSET + adcls \tmp, \tmp, #0 + +addls doesn't update flags, adcls adds carry from cmp above: + + cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? + +Condition 'ls' means carry flag is clear or zero flag is set, thus only one +case is affected: when PHYS_OFFSET == PAGE_OFFSET. + +It seems safer to remove this fixup. Bug is here for ages and nobody +complained. Let's fix it separately. + +Signed-off-by: Konstantin Khlebnikov <k.khlebnikov@samsung.com> +Reported-and-tested-by: Jassi Brar <jassisinghbrar@gmail.com> +--- + arch/arm/mm/proc-v7-3level.S | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S +index 1a24e92..b64e67c 100644 +--- a/arch/arm/mm/proc-v7-3level.S ++++ b/arch/arm/mm/proc-v7-3level.S +@@ -146,7 +146,6 @@ ENDPROC(cpu_v7_set_pte_ext) + mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits + mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits + addls \ttbr1, \ttbr1, #TTBR1_OFFSET +- adcls \tmp, \tmp, #0 + mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1 + mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits + mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits diff --git a/a/content_digest b/N1/content_digest index 72de763..4558469 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -7,11 +7,17 @@ "ref\0CALYGNiN-SHr6YJ53_deizb1VoXTBzD7dn8hcwqd4zLjx6utCDw@mail.gmail.com\0" "ref\0CABb+yY1VsEwDi5XCRkKbSNPW_+_MgL4gdAChKgX_NGHRzXq6qw@mail.gmail.com\0" "ref\020140828110300.GJ22580@arm.com\0" - "From\0k.khlebnikov@samsung.com (Konstantin Khlebnikov)\0" - "Subject\0[PATCH 1/2] ARM: LPAE: load upper bits of early TTBR0/TTBR1\0" + "From\0Konstantin Khlebnikov <k.khlebnikov@samsung.com>\0" + "Subject\0Re: [PATCH 1/2] ARM: LPAE: load upper bits of early TTBR0/TTBR1\0" "Date\0Thu, 28 Aug 2014 15:50:56 +0400\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Will Deacon <will.deacon@arm.com>" + " Jassi Brar <jassisinghbrar@gmail.com>\0" + "Cc\0Konstantin Khlebnikov <koct9i@gmail.com>" + Russell King <linux@arm.linux.org.uk> + linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org> + Vitaly Andrianov <vitalya@ti.com> + " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" + "\01:1\0" "b\0" "\n" "On 2014-08-28 15:03, Will Deacon wrote:\n" @@ -46,9 +52,10 @@ "\n" ">\n" "> Will\n" - ">\n" - "\n" - "-------------- next part --------------\n" + > + "\01:2\0" + "fn\0arm-lpae-remove-carry-flag-correction-after-adding-ttbr1_offset\0" + "b\0" "ARM: LPAE: drop wrong carry flag correction after adding TTBR1_OFFSET\n" "\n" "From: Konstantin Khlebnikov <k.khlebnikov@samsung.com>\n" @@ -89,4 +96,4 @@ " \tmov\t\\tmp, \\ttbr0, lsr #(32 - ARCH_PGD_SHIFT)\t@ upper bits\n" " \tmov\t\\ttbr0, \\ttbr0, lsl #ARCH_PGD_SHIFT\t\t@ lower bits" -59813843d8b721364b20a1ee9ce52da1aab915590424ce5a7553447546b0f8ec +7f038d8ed2bf254ab56fabec0448c18e9368fc679c9f5402909b1bb0047b6fc8
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