From: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
LKML <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org"
<jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
"computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding
Date: Fri, 05 Sep 2014 14:15:08 -0700 [thread overview]
Message-ID: <540A27DC.4010206@gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1409052224211.5472@nanos>
On 09/05/2014 01:44 PM, Thomas Gleixner wrote:
> On Fri, 5 Sep 2014, Florian Fainelli wrote:
>> On 09/05/2014 12:21 PM, Thomas Gleixner wrote:
>>> So if I understand correctly what you have is:
>>>
>>> /- GIC------------->
>>> Device-irq ---- [routing]
>>> \- BC irq chip ---->
>>>
>>> and you implement it as
>>>
>>> Device-irq ---- [BC irq chip] ---- [GIC] --->
>>> |
>>> ----------------->
>>>
>>> And the fwd mask is to tell the BC chip to use the GIC and which irq
>>> of the GIC, so it can fiddle with the GIC under the hood, right?
>>
>> The forward mask really is to tell the BCM7120 l2 interrupt controller:
>> bypass me, and output the UART interrupts directly at the GIC level, so
>> I think this does match your understanding.
>>
>> Not setting the forward mask means you would get the UART interrupts at
>> the BCM7120 l2 interrupt controller level, and have to handle them here.
>>
>> Hope this helps clarify what this funky piece of hardware does.
>
> Sigh, this stacked interrupt chip nonsense is becoming a plague.
This is a HW design that we inherited, but fortunately we might be able
to fix that in the future.
>
> So if you set that bit then the UART driver only sees the GIC as its
> interrupt controller and not the L2 thingy. So, the L2 chip only
> enables its interrupt unconditionally for that line and the
> enable/disable happens at the GIC level.
Exactly, this is completely transparent for the UART and the GIC.
>
> If that's the case, that's fine with me. It's not pretty, but at least
> it does not involve L2 fiddling indirectly with the GIC.
Absolutely, we do not have to do the arch_gic_extn thingy.
Thanks for your feedback!
--
Florian
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WARNING: multiple messages have this Message-ID (diff)
From: Florian Fainelli <f.fainelli@gmail.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>,
LKML <linux-kernel@vger.kernel.org>,
"jason@lakedaemon.net" <jason@lakedaemon.net>,
"computersforpeace@gmail.com" <computersforpeace@gmail.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding
Date: Fri, 05 Sep 2014 14:15:08 -0700 [thread overview]
Message-ID: <540A27DC.4010206@gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1409052224211.5472@nanos>
On 09/05/2014 01:44 PM, Thomas Gleixner wrote:
> On Fri, 5 Sep 2014, Florian Fainelli wrote:
>> On 09/05/2014 12:21 PM, Thomas Gleixner wrote:
>>> So if I understand correctly what you have is:
>>>
>>> /- GIC------------->
>>> Device-irq ---- [routing]
>>> \- BC irq chip ---->
>>>
>>> and you implement it as
>>>
>>> Device-irq ---- [BC irq chip] ---- [GIC] --->
>>> |
>>> ----------------->
>>>
>>> And the fwd mask is to tell the BC chip to use the GIC and which irq
>>> of the GIC, so it can fiddle with the GIC under the hood, right?
>>
>> The forward mask really is to tell the BCM7120 l2 interrupt controller:
>> bypass me, and output the UART interrupts directly at the GIC level, so
>> I think this does match your understanding.
>>
>> Not setting the forward mask means you would get the UART interrupts at
>> the BCM7120 l2 interrupt controller level, and have to handle them here.
>>
>> Hope this helps clarify what this funky piece of hardware does.
>
> Sigh, this stacked interrupt chip nonsense is becoming a plague.
This is a HW design that we inherited, but fortunately we might be able
to fix that in the future.
>
> So if you set that bit then the UART driver only sees the GIC as its
> interrupt controller and not the L2 thingy. So, the L2 chip only
> enables its interrupt unconditionally for that line and the
> enable/disable happens at the GIC level.
Exactly, this is completely transparent for the UART and the GIC.
>
> If that's the case, that's fine with me. It's not pretty, but at least
> it does not involve L2 fiddling indirectly with the GIC.
Absolutely, we do not have to do the arch_gic_extn thingy.
Thanks for your feedback!
--
Florian
next prev parent reply other threads:[~2014-09-05 21:15 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-28 22:35 [PATCH 0/2] irqchip: Broadcom BCM7120-style Level 2 interrupt controller Florian Fainelli
2014-08-28 22:35 ` [PATCH 1/2] irqchip: add " Florian Fainelli
2014-09-03 12:18 ` Thomas Gleixner
2014-09-03 16:39 ` Florian Fainelli
2014-08-28 22:35 ` [PATCH 2/2] Documentation: bcm7120-l2: Add Broadcom BCM7120-style L2 binding Florian Fainelli
[not found] ` <1409265326-7579-3-git-send-email-f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-09-03 12:13 ` Thomas Gleixner
2014-09-03 12:13 ` Thomas Gleixner
2014-09-03 12:43 ` Mark Rutland
2014-09-03 16:59 ` Florian Fainelli
[not found] ` <5407490E.7060505-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-09-05 9:05 ` Mark Rutland
2014-09-05 9:05 ` Mark Rutland
2014-09-05 18:01 ` Florian Fainelli
[not found] ` <5409FA82.6000703-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2014-09-05 19:21 ` Thomas Gleixner
2014-09-05 19:21 ` Thomas Gleixner
2014-09-05 19:57 ` Florian Fainelli
2014-09-05 19:57 ` Florian Fainelli
2014-09-05 20:44 ` Thomas Gleixner
2014-09-05 21:15 ` Florian Fainelli [this message]
2014-09-05 21:15 ` Florian Fainelli
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