[U-Boot] [PATCH 1/2] arm: vf610: lpuart: fix status register handling

[U-Boot] [PATCH 1/2] arm: vf610: lpuart: fix status register handling

[Stefan Agner]

The status register 1 (S1) is not writeable, hence we should not
write it. In order to clear the RDRF flag we only need to read
the data register.

Also, when stressing U-Boot a lot with serial input, an overflow can
occur which asserts the S1_OR flag (while not asserting the S1_RDRF
flag). To clear this flag we again just need to read the data
register, hence add this flag to the abort conditions for the while
loop.

Insert a compiler barrier to make sure reading the data register
gets executed after reading the status register.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/serial/serial_lpuart.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index da5f9a2..96173ca 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -14,6 +14,7 @@
 
 #define US1_TDRE        (1 << 7)
 #define US1_RDRF        (1 << 5)
+#define US1_OR          (1 << 3)
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
 
@@ -38,14 +39,10 @@ static void lpuart_serial_setbrg(void)
 
 static int lpuart_serial_getc(void)
 {
-	u8 status;
-
-	while (!(__raw_readb(&base->us1) & US1_RDRF))
+	while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
 		WATCHDOG_RESET();
 
-	status = __raw_readb(&base->us1);
-	status |= US1_RDRF;
-	__raw_writeb(status, &base->us1);
+	barrier();
 
 	return __raw_readb(&base->ud);
 }
-- 
2.0.4

[U-Boot] [PATCH 2/2] arm: vf610: lpuart: disable FIFO on initializaton

[Stefan Agner]

UART does not use the UART FIFO, but we should also not rely that
the UART FIFO is diabled by default. For instance, when loading
U-Boot using the boot ROMs serial downloader protocol over UART,
FIFO is enabled at U-Boot start time.

This patch disables the RX and TX FIFO, sets back their thresholds
and flushes them.

Signed-off-by: Stefan Agner <stefan@agner.ch>
---
 drivers/serial/serial_lpuart.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index 96173ca..0a5e159 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -17,6 +17,10 @@
 #define US1_OR          (1 << 3)
 #define UC2_TE          (1 << 3)
 #define UC2_RE          (1 << 2)
+#define CFIFO_TXFLUSH   (1 << 7)
+#define CFIFO_RXFLUSH   (1 << 6)
+#define SFIFO_RXOF      (1 << 2)
+#define SFIFO_RXUF      (1 << 0)
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,6 +89,12 @@ static int lpuart_serial_init(void)
 	__raw_writeb(0, &base->umodem);
 	__raw_writeb(0, &base->uc1);
 
+	/* Disable FIFO and flush buffer */
+	__raw_writeb(0x0, &base->upfifo);
+	__raw_writeb(0x0, &base->utwfifo);
+	__raw_writeb(0x1, &base->urwfifo);
+	__raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
+
 	/* provide data bits, parity, stop bit, etc */
 
 	serial_setbrg();
-- 
2.0.4

[U-Boot] [PATCH 2/2] arm: vf610: lpuart: disable FIFO on initializaton

[Stefano Babic]

On 19/08/2014 17:54, Stefan Agner wrote:
> UART does not use the UART FIFO, but we should also not rely that
> the UART FIFO is diabled by default. For instance, when loading
> U-Boot using the boot ROMs serial downloader protocol over UART,
> FIFO is enabled at U-Boot start time.
> 
> This patch disables the RX and TX FIFO, sets back their thresholds
> and flushes them.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] arm: vf610: lpuart: fix status register handling

[Stefano Babic]

On 19/08/2014 17:54, Stefan Agner wrote:
> The status register 1 (S1) is not writeable, hence we should not
> write it. In order to clear the RDRF flag we only need to read
> the data register.
> 
> Also, when stressing U-Boot a lot with serial input, an overflow can
> occur which asserts the S1_OR flag (while not asserting the S1_RDRF
> flag). To clear this flag we again just need to read the data
> register, hence add this flag to the abort conditions for the while
> loop.
> 
> Insert a compiler barrier to make sure reading the data register
> gets executed after reading the status register.
> 
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---

Applied to u-boot-imx, thanks!

Best regards,
Stefano Babic



-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================