* [U-Boot] [PATCH 0/2 v3] Add support for mx6 onchip temperature sensor @ 2014-09-01 22:48 nitin.garg at freescale.com 2014-09-01 22:48 ` [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support nitin.garg at freescale.com 2014-09-01 22:48 ` [U-Boot] [PATCH 2/2 v3] Enable SoC Temperature sensor for mx6 Sabre boards nitin.garg at freescale.com 0 siblings, 2 replies; 5+ messages in thread From: nitin.garg at freescale.com @ 2014-09-01 22:48 UTC (permalink / raw) To: u-boot From: Nitin Garg <nitin.garg@freescale.com> Add support for mx6 onchip temperature sensor and enable it for all mx6sabre boards. Nitin Garg (2): Changes since v2: - Split the patch into 2: Feature impl and board enablement Changes since v1: - Make temperature sensor feature configurable - Checkpatch fixes Add i.MX6 CPU temperature sensor support Enable SoC Temperature sensor for mx6 Sabre boards. arch/arm/cpu/armv7/mx6/soc.c | 138 +++++++- arch/arm/imx-common/cpu.c | 7 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 543 +++++++++++++++++++++++++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 9 +- include/configs/mx6sabre_common.h | 1 + 5 files changed, 694 insertions(+), 4 deletions(-) -- 1.7.9.5 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support 2014-09-01 22:48 [U-Boot] [PATCH 0/2 v3] Add support for mx6 onchip temperature sensor nitin.garg at freescale.com @ 2014-09-01 22:48 ` nitin.garg at freescale.com 2014-09-11 9:01 ` Stefano Babic 2014-09-01 22:48 ` [U-Boot] [PATCH 2/2 v3] Enable SoC Temperature sensor for mx6 Sabre boards nitin.garg at freescale.com 1 sibling, 1 reply; 5+ messages in thread From: nitin.garg at freescale.com @ 2014-09-01 22:48 UTC (permalink / raw) To: u-boot From: Nitin Garg <nitin.garg@freescale.com> i.MX6 SoC has onChip temperature sensor. Add support for this sensor. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> --- arch/arm/cpu/armv7/mx6/soc.c | 138 +++++++- arch/arm/imx-common/cpu.c | 7 +- arch/arm/include/asm/arch-mx6/crm_regs.h | 543 +++++++++++++++++++++++++++++- arch/arm/include/asm/arch-mx6/imx-regs.h | 9 +- 4 files changed, 693 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index ac84a1f..b0c1306 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -35,6 +35,16 @@ struct scu_regs { u32 fpga_rev; }; +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 80 +#define TEMPERATURE_MAX 125 +#define FACTOR1 15976 +#define FACTOR2 4297157 +#define MEASURE_FREQ 327 + +#define REG_VALUE_TO_CEL(ratio, raw) \ + ((raw_n40c - raw) * 100 / ratio - 40) + u32 get_nr_cpus(void) { struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; @@ -218,6 +228,132 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +#ifdef CONFIG_IMX6_TEMP_SENSOR +static int read_cpu_temperature(u32 *fuse) +{ + int temperature; + unsigned int ccm_ccgr2; + unsigned int reg, tmp; + unsigned int raw_25c, raw_n40c, ratio; + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse_bank1 = + (struct fuse_bank1_regs *)bank->fuse_regs; + + /* need to make sure pll3 is enabled for thermal sensor */ + if ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { + /* enable pll's power */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, + &anatop->usb1_pll_480_ctrl_set); + writel(0x80, &anatop->ana_misc2_clr); + /* wait for pll lock */ + while ((readl(&anatop->usb1_pll_480_ctrl) & + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) + ; + /* disable bypass */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, + &anatop->usb1_pll_480_ctrl_clr); + /* enable pll output */ + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, + &anatop->usb1_pll_480_ctrl_set); + } + + ccm_ccgr2 = readl(&mxc_ccm->CCGR2); + /* enable OCOTP_CTRL clock in CCGR2 */ + writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, &mxc_ccm->CCGR2); + *fuse = readl(&fuse_bank1->ana1); + + /* restore CCGR2 */ + writel(ccm_ccgr2, &mxc_ccm->CCGR2); + + if (*fuse == 0 || *fuse == 0xffffffff || (*fuse & 0xfff00000) == 0) + return TEMPERATURE_MIN; + + /* + * fuse data layout: + * [31:20] sensor value @ 25C + * [19:8] sensor value of hot + * [7:0] hot temperature value + */ + raw_25c = *fuse >> 20; + + /* + * The universal equation for thermal sensor + * is slope = 0.4297157 - (0.0015976 * 25C fuse), + * here we convert them to integer to make them + * easy for counting, FACTOR1 is 15976, + * FACTOR2 is 4297157. Our ratio = -100 * slope + */ + ratio = ((FACTOR1 * raw_25c - FACTOR2) + 50000) / 100000; + + debug("Thermal sensor with ratio = %d\n", ratio); + + raw_n40c = raw_25c + (13 * ratio) / 20; + + /* + * now we only use single measure, every time we read + * the temperature, we will power on/down anadig thermal + * module + */ + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); + + /* write measure freq */ + reg = readl(&anatop->tempsense1); + reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ; + reg |= MEASURE_FREQ; + writel(reg, &anatop->tempsense1); + + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); + + while ((readl(&anatop->tempsense0) & + BM_ANADIG_TEMPSENSE0_FINISHED) == 0) + udelay(10000); + + reg = readl(&anatop->tempsense0); + tmp = (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) + >> BP_ANADIG_TEMPSENSE0_TEMP_VALUE; + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + + if (tmp <= raw_n40c) + temperature = REG_VALUE_TO_CEL(ratio, tmp); + else + temperature = TEMPERATURE_MIN; + /* power down anatop thermal sensor */ + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); + + return temperature; +} + +void check_cpu_temperature(void) +{ + int cpu_tmp = 0; + u32 fuse = ~0; + + cpu_tmp = read_cpu_temperature(&fuse); + while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) { + if (cpu_tmp >= TEMPERATURE_HOT) { + printf("CPU is %d C, too hot to boot, waiting...\n", + cpu_tmp); + udelay(5000000); + cpu_tmp = read_cpu_temperature(&fuse); + } else { + break; + } + } + if (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) + printf("CPU: Temperature %d C\n", cpu_tmp); + else + printf("CPU: Temperature: invalid data, fuse: 0x%x\n", fuse); +} +#endif + static void set_ahb_rate(u32 val) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index ed826a0..7253d37 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -139,6 +139,11 @@ int print_cpuinfo(void) (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); + +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_TEMP_SENSOR) + check_cpu_temperature(); +#endif + printf("Reset cause: %s\n", get_reset_cause()); return 0; } diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index e67b5b9..66a7cea 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -1061,4 +1061,545 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define HW_ANADIG_REG_1P1 (0x00000110) +#define HW_ANADIG_REG_1P1_SET (0x00000114) +#define HW_ANADIG_REG_1P1_CLR (0x00000118) +#define HW_ANADIG_REG_1P1_TOG (0x0000011c) + +#define BP_ANADIG_REG_1P1_RSVD2 18 +#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC0000 +#define BF_ANADIG_REG_1P1_RSVD2(v) \ + (((v) << 18) & BM_ANADIG_REG_1P1_RSVD2) +#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000 +#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000 +#define BP_ANADIG_REG_1P1_RSVD1 13 +#define BM_ANADIG_REG_1P1_RSVD1 0x0000E000 +#define BF_ANADIG_REG_1P1_RSVD1(v) \ + (((v) << 13) & BM_ANADIG_REG_1P1_RSVD1) +#define BP_ANADIG_REG_1P1_OUTPUT_TRG 8 +#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00 +#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v) \ + (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG) +#define BM_ANADIG_REG_1P1_RSVD0 0x00000080 +#define BP_ANADIG_REG_1P1_BO_OFFSET 4 +#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070 +#define BF_ANADIG_REG_1P1_BO_OFFSET(v) \ + (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET) +#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008 +#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_3P0 (0x00000120) +#define HW_ANADIG_REG_3P0_SET (0x00000124) +#define HW_ANADIG_REG_3P0_CLR (0x00000128) +#define HW_ANADIG_REG_3P0_TOG (0x0000012c) + +#define BP_ANADIG_REG_3P0_RSVD2 18 +#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC0000 +#define BF_ANADIG_REG_3P0_RSVD2(v) \ + (((v) << 18) & BM_ANADIG_REG_3P0_RSVD2) +#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000 +#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000 +#define BP_ANADIG_REG_3P0_RSVD1 13 +#define BM_ANADIG_REG_3P0_RSVD1 0x0000E000 +#define BF_ANADIG_REG_3P0_RSVD1(v) \ + (((v) << 13) & BM_ANADIG_REG_3P0_RSVD1) +#define BP_ANADIG_REG_3P0_OUTPUT_TRG 8 +#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00 +#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v) \ + (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG) +#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080 +#define BP_ANADIG_REG_3P0_BO_OFFSET 4 +#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070 +#define BF_ANADIG_REG_3P0_BO_OFFSET(v) \ + (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET) +#define BM_ANADIG_REG_3P0_RSVD0 0x00000008 +#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_2P5 (0x00000130) +#define HW_ANADIG_REG_2P5_SET (0x00000134) +#define HW_ANADIG_REG_2P5_CLR (0x00000138) +#define HW_ANADIG_REG_2P5_TOG (0x0000013c) + +#define BP_ANADIG_REG_2P5_RSVD2 19 +#define BM_ANADIG_REG_2P5_RSVD2 0xFFF80000 +#define BF_ANADIG_REG_2P5_RSVD2(v) \ + (((v) << 19) & BM_ANADIG_REG_2P5_RSVD2) +#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000 +#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000 +#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000 +#define BP_ANADIG_REG_2P5_RSVD1 13 +#define BM_ANADIG_REG_2P5_RSVD1 0x0000E000 +#define BF_ANADIG_REG_2P5_RSVD1(v) \ + (((v) << 13) & BM_ANADIG_REG_2P5_RSVD1) +#define BP_ANADIG_REG_2P5_OUTPUT_TRG 8 +#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00 +#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v) \ + (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG) +#define BM_ANADIG_REG_2P5_RSVD0 0x00000080 +#define BP_ANADIG_REG_2P5_BO_OFFSET 4 +#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070 +#define BF_ANADIG_REG_2P5_BO_OFFSET(v) \ + (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET) +#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008 +#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004 +#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002 +#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001 + +#define HW_ANADIG_REG_CORE (0x00000140) +#define HW_ANADIG_REG_CORE_SET (0x00000144) +#define HW_ANADIG_REG_CORE_CLR (0x00000148) +#define HW_ANADIG_REG_CORE_TOG (0x0000014c) + +#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000 +#define BM_ANADIG_REG_CORE_RSVD0 0x40000000 +#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 +#define BP_ANADIG_REG_CORE_RAMP_RATE 27 +#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000 +#define BF_ANADIG_REG_CORE_RAMP_RATE(v) \ + (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE) +#define BP_ANADIG_REG_CORE_REG2_ADJ 23 +#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000 +#define BF_ANADIG_REG_CORE_REG2_ADJ(v) \ + (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ) +#define BP_ANADIG_REG_CORE_REG2_TRG 18 +#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000 +#define BF_ANADIG_REG_CORE_REG2_TRG(v) \ + (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG) +#define BP_ANADIG_REG_CORE_REG1_ADJ 14 +#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000 +#define BF_ANADIG_REG_CORE_REG1_ADJ(v) \ + (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ) +#define BP_ANADIG_REG_CORE_REG1_TRG 9 +#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00 +#define BF_ANADIG_REG_CORE_REG1_TRG(v) \ + (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG) +#define BP_ANADIG_REG_CORE_REG0_ADJ 5 +#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0 +#define BF_ANADIG_REG_CORE_REG0_ADJ(v) \ + (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ) +#define BP_ANADIG_REG_CORE_REG0_TRG 0 +#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F +#define BF_ANADIG_REG_CORE_REG0_TRG(v) \ + (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG) + +#define HW_ANADIG_ANA_MISC0 (0x00000150) +#define HW_ANADIG_ANA_MISC0_SET (0x00000154) +#define HW_ANADIG_ANA_MISC0_CLR (0x00000158) +#define HW_ANADIG_ANA_MISC0_TOG (0x0000015c) + +#define BP_ANADIG_ANA_MISC0_RSVD2 29 +#define BM_ANADIG_ANA_MISC0_RSVD2 0xE0000000 +#define BF_ANADIG_ANA_MISC0_RSVD2(v) \ + (((v) << 29) & BM_ANADIG_ANA_MISC0_RSVD2) +#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 +#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000 +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ + (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) +#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000 +#define BP_ANADIG_ANA_MISC0_ANAMUX 21 +#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000 +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ + (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX) +#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000 +#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 +#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000 +#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ + (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000 +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000 +#define BP_ANADIG_ANA_MISC0_OSC_I 14 +#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ + (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I) +#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000 +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000 +#define BP_ANADIG_ANA_MISC0_RSVD0 10 +#define BM_ANADIG_ANA_MISC0_RSVD0 0x00000C00 +#define BF_ANADIG_ANA_MISC0_RSVD0(v) \ + (((v) << 10) & BM_ANADIG_ANA_MISC0_RSVD0) +#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 +#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 +#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \ + (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080 +#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070 +#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ + (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004 +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002 +#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001 + +#define HW_ANADIG_ANA_MISC1 (0x00000160) +#define HW_ANADIG_ANA_MISC1_SET (0x00000164) +#define HW_ANADIG_ANA_MISC1_CLR (0x00000168) +#define HW_ANADIG_ANA_MISC1_TOG (0x0000016c) + +#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000 +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 +#define BP_ANADIG_ANA_MISC1_RSVD0 14 +#define BM_ANADIG_ANA_MISC1_RSVD0 0x1FFFC000 +#define BF_ANADIG_ANA_MISC1_RSVD0(v) \ + (((v) << 14) & BM_ANADIG_ANA_MISC1_RSVD0) +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000 +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000 +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800 +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400 +#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 +#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 +#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ + (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) +#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ + (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) + +#define HW_ANADIG_ANA_MISC2 (0x00000170) +#define HW_ANADIG_ANA_MISC2_SET (0x00000174) +#define HW_ANADIG_ANA_MISC2_CLR (0x00000178) +#define HW_ANADIG_ANA_MISC2_TOG (0x0000017c) + +#define BP_ANADIG_ANA_MISC2_CONTROL3 30 +#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 +#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ + (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3) +#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 +#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 +#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ + (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 +#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ + (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) +#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 +#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 +#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ + (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) +#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 +#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 +#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000 +#define BM_ANADIG_ANA_MISC2_RSVD2 0x00100000 +#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000 +#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 +#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 +#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ + (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000 +#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000 +#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000 +#define BM_ANADIG_ANA_MISC2_RSVD1 0x00001000 +#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800 +#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 +#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 +#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ + (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080 +#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040 +#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020 +#define BM_ANADIG_ANA_MISC2_RSVD0 0x00000010 +#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008 +#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 +#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007 +#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ + (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) + +#define HW_ANADIG_TEMPSENSE0 (0x00000180) +#define HW_ANADIG_TEMPSENSE0_SET (0x00000184) +#define HW_ANADIG_TEMPSENSE0_CLR (0x00000188) +#define HW_ANADIG_TEMPSENSE0_TOG (0x0000018c) + +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000 +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ + (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00 +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ + (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BM_ANADIG_TEMPSENSE0_RSVD0 0x00000080 +#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040 +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 +#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038 +#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ + (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ) +#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004 +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002 +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001 + +#define HW_ANADIG_TEMPSENSE1 (0x00000190) +#define HW_ANADIG_TEMPSENSE1_SET (0x00000194) +#define HW_ANADIG_TEMPSENSE1_CLR (0x00000198) +#define HW_ANADIG_TEMPSENSE1_TOG (0x0000019c) + +#define BP_ANADIG_TEMPSENSE1_RSVD0 16 +#define BM_ANADIG_TEMPSENSE1_RSVD0 0xFFFF0000 +#define BF_ANADIG_TEMPSENSE1_RSVD0(v) \ + (((v) << 16) & BM_ANADIG_TEMPSENSE1_RSVD0) +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ + (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) + +#define HW_ANADIG_USB1_VBUS_DETECT (0x000001a0) +#define HW_ANADIG_USB1_VBUS_DETECT_SET (0x000001a4) +#define HW_ANADIG_USB1_VBUS_DETECT_CLR (0x000001a8) +#define HW_ANADIG_USB1_VBUS_DETECT_TOG (0x000001ac) + +#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD2 28 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD2 0x70000000 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD2(v) \ + (((v) << 28) & BM_ANADIG_USB1_VBUS_DETECT_RSVD2) +#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000 +#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD1 21 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD1 0x03E00000 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB1_VBUS_DETECT_RSVD1) +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD0 8 +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD0 0x0003FF00 +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD0(v) \ + (((v) << 8) & BM_ANADIG_USB1_VBUS_DETECT_RSVD0) +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080 +#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040 +#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020 +#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008 +#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0 +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 +#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) \ + (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH) + +#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0) +#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4) +#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8) +#define HW_ANADIG_USB1_CHRG_DETECT_TOG (0x000001bc) + +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD2 24 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD2 0xFF000000 +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD2(v) \ + (((v) << 24) & BM_ANADIG_USB1_CHRG_DETECT_RSVD2) +#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000 +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD1 21 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD1 0x00600000 +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB1_CHRG_DETECT_RSVD1) +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000 +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD0 1 +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD0 0x0003FFFE +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_USB1_CHRG_DETECT_RSVD0) +#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001 + +#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0) +#define HW_ANADIG_USB1_VBUS_DET_STAT_SET (0x000001c4) +#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR (0x000001c8) +#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG (0x000001cc) + +#define BP_ANADIG_USB1_VBUS_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB1_VBUS_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0) +#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008 +#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004 +#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002 +#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001 + +#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0) +#define HW_ANADIG_USB1_CHRG_DET_STAT_SET (0x000001d4) +#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR (0x000001d8) +#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG (0x000001dc) + +#define BP_ANADIG_USB1_CHRG_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB1_CHRG_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0) +#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008 +#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004 +#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 +#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 + +#define HW_ANADIG_USB1_LOOPBACK (0x000001e0) +#define HW_ANADIG_USB1_LOOPBACK_SET (0x000001e4) +#define HW_ANADIG_USB1_LOOPBACK_CLR (0x000001e8) +#define HW_ANADIG_USB1_LOOPBACK_TOG (0x000001ec) + +#define BP_ANADIG_USB1_LOOPBACK_RSVD0 9 +#define BM_ANADIG_USB1_LOOPBACK_RSVD0 0xFFFFFE00 +#define BF_ANADIG_USB1_LOOPBACK_RSVD0(v) \ + (((v) << 9) & BM_ANADIG_USB1_LOOPBACK_RSVD0) +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100 +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002 +#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001 + +#define HW_ANADIG_USB1_MISC (0x000001f0) +#define HW_ANADIG_USB1_MISC_SET (0x000001f4) +#define HW_ANADIG_USB1_MISC_CLR (0x000001f8) +#define HW_ANADIG_USB1_MISC_TOG (0x000001fc) + +#define BM_ANADIG_USB1_MISC_RSVD1 0x80000000 +#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000 +#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000 +#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000 +#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000 +#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000 +#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000 +#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000 +#define BP_ANADIG_USB1_MISC_RSVD0 2 +#define BM_ANADIG_USB1_MISC_RSVD0 0x00FFFFFC +#define BF_ANADIG_USB1_MISC_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB1_MISC_RSVD0) +#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002 +#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001 + +#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200) +#define HW_ANADIG_USB2_VBUS_DETECT_SET (0x00000204) +#define HW_ANADIG_USB2_VBUS_DETECT_CLR (0x00000208) +#define HW_ANADIG_USB2_VBUS_DETECT_TOG (0x0000020c) + +#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD2 28 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD2 0x70000000 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD2(v) \ + (((v) << 28) & BM_ANADIG_USB2_VBUS_DETECT_RSVD2) +#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000 +#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD1 21 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD1 0x03E00000 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB2_VBUS_DETECT_RSVD1) +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD0 3 +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD0 0x0003FFF8 +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD0(v) \ + (((v) << 3) & BM_ANADIG_USB2_VBUS_DETECT_RSVD0) +#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0 +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 +#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) \ + (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH) + +#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) +#define HW_ANADIG_USB2_CHRG_DETECT_SET (0x00000214) +#define HW_ANADIG_USB2_CHRG_DETECT_CLR (0x00000218) +#define HW_ANADIG_USB2_CHRG_DETECT_TOG (0x0000021c) + +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD2 24 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD2 0xFF000000 +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD2(v) \ + (((v) << 24) & BM_ANADIG_USB2_CHRG_DETECT_RSVD2) +#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000 +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD1 21 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD1 0x00600000 +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD1(v) \ + (((v) << 21) & BM_ANADIG_USB2_CHRG_DETECT_RSVD1) +#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000 +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD0 1 +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD0 0x0003FFFE +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD0(v) \ + (((v) << 1) & BM_ANADIG_USB2_CHRG_DETECT_RSVD0) +#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001 + +#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220) +#define HW_ANADIG_USB2_VBUS_DET_STAT_SET (0x00000224) +#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR (0x00000228) +#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG (0x0000022c) + +#define BP_ANADIG_USB2_VBUS_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB2_VBUS_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0) +#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008 +#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004 +#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002 +#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001 + +#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230) +#define HW_ANADIG_USB2_CHRG_DET_STAT_SET (0x00000234) +#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR (0x00000238) +#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG (0x0000023c) + +#define BP_ANADIG_USB2_CHRG_DET_STAT_RSVD0 4 +#define BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 +#define BF_ANADIG_USB2_CHRG_DET_STAT_RSVD0(v) \ + (((v) << 4) & BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0) +#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008 +#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004 +#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 +#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 + +#define HW_ANADIG_USB2_LOOPBACK (0x00000240) +#define HW_ANADIG_USB2_LOOPBACK_SET (0x00000244) +#define HW_ANADIG_USB2_LOOPBACK_CLR (0x00000248) +#define HW_ANADIG_USB2_LOOPBACK_TOG (0x0000024c) + +#define BP_ANADIG_USB2_LOOPBACK_RSVD0 9 +#define BM_ANADIG_USB2_LOOPBACK_RSVD0 0xFFFFFE00 +#define BF_ANADIG_USB2_LOOPBACK_RSVD0(v) \ + (((v) << 9) & BM_ANADIG_USB2_LOOPBACK_RSVD0) +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100 +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002 +#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001 + +#define HW_ANADIG_USB2_MISC (0x00000250) +#define HW_ANADIG_USB2_MISC_SET (0x00000254) +#define HW_ANADIG_USB2_MISC_CLR (0x00000258) +#define HW_ANADIG_USB2_MISC_TOG (0x0000025c) + +#define BM_ANADIG_USB2_MISC_RSVD1 0x80000000 +#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000 +#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000 +#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000 +#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000 +#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000 +#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000 +#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000 +#define BP_ANADIG_USB2_MISC_RSVD0 2 +#define BM_ANADIG_USB2_MISC_RSVD0 0x00FFFFFC +#define BF_ANADIG_USB2_MISC_RSVD0(v) \ + (((v) << 2) & BM_ANADIG_USB2_MISC_RSVD0) +#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002 +#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001 + +#define HW_ANADIG_DIGPROG (0x00000260) + +#define BP_ANADIG_DIGPROG_RSVD 24 +#define BM_ANADIG_DIGPROG_RSVD 0xFF000000 +#define BF_ANADIG_DIGPROG_RSVD(v) \ + (((v) << 24) & BM_ANADIG_DIGPROG_RSVD) +#define BP_ANADIG_DIGPROG_MAJOR 8 +#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00 +#define BF_ANADIG_DIGPROG_MAJOR(v) \ + (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR) +#define BP_ANADIG_DIGPROG_MINOR 0 +#define BM_ANADIG_DIGPROG_MINOR 0x000000FF +#define BF_ANADIG_DIGPROG_MINOR(v) \ + (((v) << 0) & BM_ANADIG_DIGPROG_MINOR) + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 2631beb..4b44095 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -587,6 +587,12 @@ struct fuse_bank0_regs { u32 rsvd7[4]; }; +struct fuse_bank1_regs { + u32 mem[0x18]; + u32 ana1; + u32 ana2; +}; + #ifdef CONFIG_MX6SX struct fuse_bank4_regs { u32 sjc_resp_low; @@ -805,5 +811,6 @@ struct pwm_regs { u32 pr; u32 cnr; }; +void check_cpu_temperature(void); #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support 2014-09-01 22:48 ` [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support nitin.garg at freescale.com @ 2014-09-11 9:01 ` Stefano Babic 2014-09-16 18:43 ` Nitin Garg 0 siblings, 1 reply; 5+ messages in thread From: Stefano Babic @ 2014-09-11 9:01 UTC (permalink / raw) To: u-boot Hi Nitin, On 02/09/2014 00:48, nitin.garg at freescale.com wrote: > From: Nitin Garg <nitin.garg@freescale.com> > > i.MX6 SoC has onChip temperature sensor. Add support > for this sensor. > > Signed-off-by: Nitin Garg <nitin.garg@freescale.com> > --- > arch/arm/cpu/armv7/mx6/soc.c | 138 +++++++- > arch/arm/imx-common/cpu.c | 7 +- > arch/arm/include/asm/arch-mx6/crm_regs.h | 543 +++++++++++++++++++++++++++++- > arch/arm/include/asm/arch-mx6/imx-regs.h | 9 +- > 4 files changed, 693 insertions(+), 4 deletions(-) > I tend to consider this as a driver instead of a couple of functions to read/check temperature. Hiding this code inside cpu code does not get an overview about which API is used. If another SOC (not necessarily Freescale) will add such kind of functionality, we will have probably a different API. I would prefer, without reinventing the wheel, to follow the kernel approach and move this code into a driver, let's say into drivers/thermal. Feel free to add this directory to u-boot tree. A name as imx-thermal as in kernel looks to me appropriate for your code. > diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c > index ac84a1f..b0c1306 100644 > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -2,7 +2,7 @@ > * (C) Copyright 2007 > * Sascha Hauer, Pengutronix > * > - * (C) Copyright 2009 Freescale Semiconductor, Inc. > + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. > * > * SPDX-License-Identifier: GPL-2.0+ > */ > @@ -35,6 +35,16 @@ struct scu_regs { > u32 fpga_rev; > }; > > +#define TEMPERATURE_MIN -40 > +#define TEMPERATURE_HOT 80 > +#define TEMPERATURE_MAX 125 > +#define FACTOR1 15976 > +#define FACTOR2 4297157 > +#define MEASURE_FREQ 327 > + > +#define REG_VALUE_TO_CEL(ratio, raw) \ > + ((raw_n40c - raw) * 100 / ratio - 40) > + > u32 get_nr_cpus(void) > { > struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; > @@ -218,6 +228,132 @@ static void imx_set_wdog_powerdown(bool enable) > writew(enable, &wdog2->wmcr); > } > > +#ifdef CONFIG_IMX6_TEMP_SENSOR TEMP is rather a misleading name. It can be confused with temporary. Maybe CONFIG_IMX_THERMAL or CONFIG_IMX_THERMAL_SENSOR ? > +static int read_cpu_temperature(u32 *fuse) > +{ > + int temperature; > + unsigned int ccm_ccgr2; > + unsigned int reg, tmp; > + unsigned int raw_25c, raw_n40c, ratio; > + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; > + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; > + struct fuse_bank *bank = &ocotp->bank[1]; > + struct fuse_bank1_regs *fuse_bank1 = > + (struct fuse_bank1_regs *)bank->fuse_regs; > + > + /* need to make sure pll3 is enabled for thermal sensor */ The code to enable a clock should go into armv7/mx6/clock.c. > + if ((readl(&anatop->usb1_pll_480_ctrl) & > + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { > + /* enable pll's power */ > + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, > + &anatop->usb1_pll_480_ctrl_set); > + writel(0x80, &anatop->ana_misc2_clr); > + /* wait for pll lock */ > + while ((readl(&anatop->usb1_pll_480_ctrl) & > + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) > + ; > + /* disable bypass */ > + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, > + &anatop->usb1_pll_480_ctrl_clr); > + /* enable pll output */ > + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, > + &anatop->usb1_pll_480_ctrl_set); > + } > + > + ccm_ccgr2 = readl(&mxc_ccm->CCGR2); > + /* enable OCOTP_CTRL clock in CCGR2 */ > + writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, &mxc_ccm->CCGR2); You are readding the same code we have already merged. We have a ocotp driver in u-boot, and this uses enable_ocotp_clk() to enable and disable the clock. Please use also the functions provide by the ocotp driver. I suggest you add a Kconfig rule to make this driver dependend on ocotp. > + *fuse = readl(&fuse_bank1->ana1); > + > + /* restore CCGR2 */ > + writel(ccm_ccgr2, &mxc_ccm->CCGR2); > + > + if (*fuse == 0 || *fuse == 0xffffffff || (*fuse & 0xfff00000) == 0) > + return TEMPERATURE_MIN; > + Does it mean invalid values ? According to manual, the register is split into three different regions (Room, Hot_count, Hot_temp) and I am wondering we can simply compare the whole register. If your check means that you are reading invalid or not expected values, an error should be reported instead of falling back to the minimal temperature. > + /* > + * fuse data layout: > + * [31:20] sensor value @ 25C > + * [19:8] sensor value of hot > + * [7:0] hot temperature value > + */ > + raw_25c = *fuse >> 20; > + > + /* > + * The universal equation for thermal sensor > + * is slope = 0.4297157 - (0.0015976 * 25C fuse), > + * here we convert them to integer to make them > + * easy for counting, FACTOR1 is 15976, > + * FACTOR2 is 4297157. Our ratio = -100 * slope You do not need you repeat the values for FACTORx in comments - they can be defined in the file. > + */ > + ratio = ((FACTOR1 * raw_25c - FACTOR2) + 50000) / 100000; I think it would be better you do as in kernel, where it is explained which formulas are involved with FACTORx. You are making also an implicit round up to next FACTOR0, that is not explained here. > + > + debug("Thermal sensor with ratio = %d\n", ratio); > + > + raw_n40c = raw_25c + (13 * ratio) / 20; Where are coming 13 and 20 ? Is there any reason why this computation is slightly different as in linux kernel ? If it is possible, it will be better to stick with the kernel implementation, allowing us in future an easier porting of fixes from the kernel. And add in your commit message which is your kernel version where you get the code (better with a commit-id). > + > + /* > + * now we only use single measure, every time we read > + * the temperature, we will power on/down anadig thermal > + * module > + */ > + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); > + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); > + > + /* write measure freq */ > + reg = readl(&anatop->tempsense1); > + reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ; > + reg |= MEASURE_FREQ; > + writel(reg, &anatop->tempsense1); > + > + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); > + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); > + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); > + > + while ((readl(&anatop->tempsense0) & > + BM_ANADIG_TEMPSENSE0_FINISHED) == 0) > + udelay(10000); > + > + reg = readl(&anatop->tempsense0); > + tmp = (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) > + >> BP_ANADIG_TEMPSENSE0_TEMP_VALUE; > + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); > + > + if (tmp <= raw_n40c) > + temperature = REG_VALUE_TO_CEL(ratio, tmp); > + else > + temperature = TEMPERATURE_MIN; > + /* power down anatop thermal sensor */ > + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); > + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); > + > + return temperature; > +} > + > +void check_cpu_temperature(void) > +{ > + int cpu_tmp = 0; > + u32 fuse = ~0; > + > + cpu_tmp = read_cpu_temperature(&fuse); > + while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) { > + if (cpu_tmp >= TEMPERATURE_HOT) { > + printf("CPU is %d C, too hot to boot, waiting...\n", > + cpu_tmp); > + udelay(5000000); > + cpu_tmp = read_cpu_temperature(&fuse); > + } else { > + break; > + } I am asking myself if there are good reasons why the temperature will go down. Should we not call hang() here ? Or does the cpu become colder in this loop, then calling simply udelay ? > + } > + if (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) > + printf("CPU: Temperature %d C\n", cpu_tmp); > + else > + printf("CPU: Temperature: invalid data, fuse: 0x%x\n", fuse); > +} > +#endif > + > static void set_ahb_rate(u32 val) > { > struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c > index ed826a0..7253d37 100644 > --- a/arch/arm/imx-common/cpu.c > +++ b/arch/arm/imx-common/cpu.c > @@ -2,7 +2,7 @@ > * (C) Copyright 2007 > * Sascha Hauer, Pengutronix > * > - * (C) Copyright 2009 Freescale Semiconductor, Inc. > + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. > * > * SPDX-License-Identifier: GPL-2.0+ > */ > @@ -139,6 +139,11 @@ int print_cpuinfo(void) > (cpurev & 0x000F0) >> 4, > (cpurev & 0x0000F) >> 0, > mxc_get_clock(MXC_ARM_CLK) / 1000000); > + > +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_TEMP_SENSOR) > + check_cpu_temperature(); > +#endif > + > printf("Reset cause: %s\n", get_reset_cause()); > return 0; > } > diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h > index e67b5b9..66a7cea 100644 > --- a/arch/arm/include/asm/arch-mx6/crm_regs.h > +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h > @@ -1,5 +1,5 @@ > /* > - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. > + * Copyright 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. > * > * SPDX-License-Identifier: GPL-2.0+ > */ > @@ -1061,4 +1061,545 @@ struct mxc_ccm_reg { > #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ > (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) > > +#define HW_ANADIG_REG_1P1 (0x00000110) > +#define HW_ANADIG_REG_1P1_SET (0x00000114) > +#define HW_ANADIG_REG_1P1_CLR (0x00000118) > +#define HW_ANADIG_REG_1P1_TOG (0x0000011c) > + > +#define BP_ANADIG_REG_1P1_RSVD2 18 > +#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC0000 > +#define BF_ANADIG_REG_1P1_RSVD2(v) \ > + (((v) << 18) & BM_ANADIG_REG_1P1_RSVD2) > +#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000 > +#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000 > +#define BP_ANADIG_REG_1P1_RSVD1 13 > +#define BM_ANADIG_REG_1P1_RSVD1 0x0000E000 > +#define BF_ANADIG_REG_1P1_RSVD1(v) \ > + (((v) << 13) & BM_ANADIG_REG_1P1_RSVD1) > +#define BP_ANADIG_REG_1P1_OUTPUT_TRG 8 > +#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00 > +#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v) \ > + (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG) > +#define BM_ANADIG_REG_1P1_RSVD0 0x00000080 > +#define BP_ANADIG_REG_1P1_BO_OFFSET 4 > +#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070 > +#define BF_ANADIG_REG_1P1_BO_OFFSET(v) \ > + (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET) > +#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008 > +#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004 > +#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002 > +#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001 > + > +#define HW_ANADIG_REG_3P0 (0x00000120) > +#define HW_ANADIG_REG_3P0_SET (0x00000124) > +#define HW_ANADIG_REG_3P0_CLR (0x00000128) > +#define HW_ANADIG_REG_3P0_TOG (0x0000012c) > + > +#define BP_ANADIG_REG_3P0_RSVD2 18 > +#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC0000 > +#define BF_ANADIG_REG_3P0_RSVD2(v) \ > + (((v) << 18) & BM_ANADIG_REG_3P0_RSVD2) > +#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000 > +#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000 > +#define BP_ANADIG_REG_3P0_RSVD1 13 > +#define BM_ANADIG_REG_3P0_RSVD1 0x0000E000 > +#define BF_ANADIG_REG_3P0_RSVD1(v) \ > + (((v) << 13) & BM_ANADIG_REG_3P0_RSVD1) > +#define BP_ANADIG_REG_3P0_OUTPUT_TRG 8 > +#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00 > +#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v) \ > + (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG) > +#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080 > +#define BP_ANADIG_REG_3P0_BO_OFFSET 4 > +#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070 > +#define BF_ANADIG_REG_3P0_BO_OFFSET(v) \ > + (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET) > +#define BM_ANADIG_REG_3P0_RSVD0 0x00000008 > +#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004 > +#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002 > +#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001 > + > +#define HW_ANADIG_REG_2P5 (0x00000130) > +#define HW_ANADIG_REG_2P5_SET (0x00000134) > +#define HW_ANADIG_REG_2P5_CLR (0x00000138) > +#define HW_ANADIG_REG_2P5_TOG (0x0000013c) > + > +#define BP_ANADIG_REG_2P5_RSVD2 19 > +#define BM_ANADIG_REG_2P5_RSVD2 0xFFF80000 > +#define BF_ANADIG_REG_2P5_RSVD2(v) \ > + (((v) << 19) & BM_ANADIG_REG_2P5_RSVD2) > +#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000 > +#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000 > +#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000 > +#define BP_ANADIG_REG_2P5_RSVD1 13 > +#define BM_ANADIG_REG_2P5_RSVD1 0x0000E000 > +#define BF_ANADIG_REG_2P5_RSVD1(v) \ > + (((v) << 13) & BM_ANADIG_REG_2P5_RSVD1) > +#define BP_ANADIG_REG_2P5_OUTPUT_TRG 8 > +#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00 > +#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v) \ > + (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG) > +#define BM_ANADIG_REG_2P5_RSVD0 0x00000080 > +#define BP_ANADIG_REG_2P5_BO_OFFSET 4 > +#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070 > +#define BF_ANADIG_REG_2P5_BO_OFFSET(v) \ > + (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET) > +#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008 > +#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004 > +#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002 > +#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001 > + > +#define HW_ANADIG_REG_CORE (0x00000140) > +#define HW_ANADIG_REG_CORE_SET (0x00000144) > +#define HW_ANADIG_REG_CORE_CLR (0x00000148) > +#define HW_ANADIG_REG_CORE_TOG (0x0000014c) > + > +#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000 > +#define BM_ANADIG_REG_CORE_RSVD0 0x40000000 > +#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 > +#define BP_ANADIG_REG_CORE_RAMP_RATE 27 > +#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000 > +#define BF_ANADIG_REG_CORE_RAMP_RATE(v) \ > + (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE) > +#define BP_ANADIG_REG_CORE_REG2_ADJ 23 > +#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000 > +#define BF_ANADIG_REG_CORE_REG2_ADJ(v) \ > + (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ) > +#define BP_ANADIG_REG_CORE_REG2_TRG 18 > +#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000 > +#define BF_ANADIG_REG_CORE_REG2_TRG(v) \ > + (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG) > +#define BP_ANADIG_REG_CORE_REG1_ADJ 14 > +#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000 > +#define BF_ANADIG_REG_CORE_REG1_ADJ(v) \ > + (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ) > +#define BP_ANADIG_REG_CORE_REG1_TRG 9 > +#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00 > +#define BF_ANADIG_REG_CORE_REG1_TRG(v) \ > + (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG) > +#define BP_ANADIG_REG_CORE_REG0_ADJ 5 > +#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0 > +#define BF_ANADIG_REG_CORE_REG0_ADJ(v) \ > + (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ) > +#define BP_ANADIG_REG_CORE_REG0_TRG 0 > +#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F > +#define BF_ANADIG_REG_CORE_REG0_TRG(v) \ > + (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG) > + > +#define HW_ANADIG_ANA_MISC0 (0x00000150) > +#define HW_ANADIG_ANA_MISC0_SET (0x00000154) > +#define HW_ANADIG_ANA_MISC0_CLR (0x00000158) > +#define HW_ANADIG_ANA_MISC0_TOG (0x0000015c) > + > +#define BP_ANADIG_ANA_MISC0_RSVD2 29 > +#define BM_ANADIG_ANA_MISC0_RSVD2 0xE0000000 > +#define BF_ANADIG_ANA_MISC0_RSVD2(v) \ > + (((v) << 29) & BM_ANADIG_ANA_MISC0_RSVD2) > +#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 > +#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000 > +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ > + (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) > +#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000 > +#define BP_ANADIG_ANA_MISC0_ANAMUX 21 > +#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000 > +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ > + (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX) > +#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000 > +#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 > +#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000 > +#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ > + (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) > +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000 > +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000 > +#define BP_ANADIG_ANA_MISC0_OSC_I 14 > +#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 > +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ > + (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I) > +#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000 > +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000 > +#define BP_ANADIG_ANA_MISC0_RSVD0 10 > +#define BM_ANADIG_ANA_MISC0_RSVD0 0x00000C00 > +#define BF_ANADIG_ANA_MISC0_RSVD0(v) \ > + (((v) << 10) & BM_ANADIG_ANA_MISC0_RSVD0) > +#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 > +#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 > +#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \ > + (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) > +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080 > +#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 > +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070 > +#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ > + (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) > +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 > +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004 > +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002 > +#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001 > + > +#define HW_ANADIG_ANA_MISC1 (0x00000160) > +#define HW_ANADIG_ANA_MISC1_SET (0x00000164) > +#define HW_ANADIG_ANA_MISC1_CLR (0x00000168) > +#define HW_ANADIG_ANA_MISC1_TOG (0x0000016c) > + > +#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000 > +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 > +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 > +#define BP_ANADIG_ANA_MISC1_RSVD0 14 > +#define BM_ANADIG_ANA_MISC1_RSVD0 0x1FFFC000 > +#define BF_ANADIG_ANA_MISC1_RSVD0(v) \ > + (((v) << 14) & BM_ANADIG_ANA_MISC1_RSVD0) > +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000 > +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000 > +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800 > +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400 > +#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 > +#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 > +#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ > + (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) > +#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 > +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F > +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ > + (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) > + > +#define HW_ANADIG_ANA_MISC2 (0x00000170) > +#define HW_ANADIG_ANA_MISC2_SET (0x00000174) > +#define HW_ANADIG_ANA_MISC2_CLR (0x00000178) > +#define HW_ANADIG_ANA_MISC2_TOG (0x0000017c) > + > +#define BP_ANADIG_ANA_MISC2_CONTROL3 30 > +#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 > +#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ > + (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3) > +#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 > +#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 > +#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ > + (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) > +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 > +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 > +#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ > + (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) > +#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 > +#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 > +#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ > + (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) > +#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 > +#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 > +#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000 > +#define BM_ANADIG_ANA_MISC2_RSVD2 0x00100000 > +#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000 > +#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 > +#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 > +#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ > + (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) > +#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000 > +#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000 > +#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000 > +#define BM_ANADIG_ANA_MISC2_RSVD1 0x00001000 > +#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800 > +#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 > +#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 > +#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ > + (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) > +#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080 > +#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040 > +#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020 > +#define BM_ANADIG_ANA_MISC2_RSVD0 0x00000010 > +#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008 > +#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 > +#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007 > +#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ > + (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) > + > +#define HW_ANADIG_TEMPSENSE0 (0x00000180) > +#define HW_ANADIG_TEMPSENSE0_SET (0x00000184) > +#define HW_ANADIG_TEMPSENSE0_CLR (0x00000188) > +#define HW_ANADIG_TEMPSENSE0_TOG (0x0000018c) > + > +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 > +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000 > +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ > + (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) > +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 > +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00 > +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ > + (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) > +#define BM_ANADIG_TEMPSENSE0_RSVD0 0x00000080 > +#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040 > +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 > +#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038 > +#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ > + (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ) > +#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004 > +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002 > +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001 > + > +#define HW_ANADIG_TEMPSENSE1 (0x00000190) > +#define HW_ANADIG_TEMPSENSE1_SET (0x00000194) > +#define HW_ANADIG_TEMPSENSE1_CLR (0x00000198) > +#define HW_ANADIG_TEMPSENSE1_TOG (0x0000019c) > + > +#define BP_ANADIG_TEMPSENSE1_RSVD0 16 > +#define BM_ANADIG_TEMPSENSE1_RSVD0 0xFFFF0000 > +#define BF_ANADIG_TEMPSENSE1_RSVD0(v) \ > + (((v) << 16) & BM_ANADIG_TEMPSENSE1_RSVD0) > +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 > +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF > +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ > + (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) > + > +#define HW_ANADIG_USB1_VBUS_DETECT (0x000001a0) > +#define HW_ANADIG_USB1_VBUS_DETECT_SET (0x000001a4) > +#define HW_ANADIG_USB1_VBUS_DETECT_CLR (0x000001a8) > +#define HW_ANADIG_USB1_VBUS_DETECT_TOG (0x000001ac) > + > +#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 > +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD2 28 > +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD2 0x70000000 > +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD2(v) \ > + (((v) << 28) & BM_ANADIG_USB1_VBUS_DETECT_RSVD2) > +#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000 > +#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 > +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD1 21 > +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD1 0x03E00000 > +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD1(v) \ > + (((v) << 21) & BM_ANADIG_USB1_VBUS_DETECT_RSVD1) > +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 > +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 > +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 > +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD0 8 > +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD0 0x0003FF00 > +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD0(v) \ > + (((v) << 8) & BM_ANADIG_USB1_VBUS_DETECT_RSVD0) > +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080 > +#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040 > +#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020 > +#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010 > +#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008 > +#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0 > +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 > +#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) \ > + (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH) > + I disagree with these changes. You are adding a temperature sensors, and we are waiting here all changes to make this sensor working. But I see a lot of changes related to USB, and they, if required, should be posted in a separate patch explaining what they are fixing. > +#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0) > +#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4) > +#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8) > +#define HW_ANADIG_USB1_CHRG_DETECT_TOG (0x000001bc) > + > +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD2 24 > +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD2 0xFF000000 > +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD2(v) \ > + (((v) << 24) & BM_ANADIG_USB1_CHRG_DETECT_RSVD2) > +#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000 > +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD1 21 > +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD1 0x00600000 > +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD1(v) \ > + (((v) << 21) & BM_ANADIG_USB1_CHRG_DETECT_RSVD1) > +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 > +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 > +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000 > +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD0 1 > +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD0 0x0003FFFE > +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD0(v) \ > + (((v) << 1) & BM_ANADIG_USB1_CHRG_DETECT_RSVD0) > +#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001 > + > +#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0) > +#define HW_ANADIG_USB1_VBUS_DET_STAT_SET (0x000001c4) > +#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR (0x000001c8) > +#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG (0x000001cc) > + > +#define BP_ANADIG_USB1_VBUS_DET_STAT_RSVD0 4 > +#define BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 > +#define BF_ANADIG_USB1_VBUS_DET_STAT_RSVD0(v) \ > + (((v) << 4) & BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0) > +#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008 > +#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004 > +#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002 > +#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001 > + > +#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0) > +#define HW_ANADIG_USB1_CHRG_DET_STAT_SET (0x000001d4) > +#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR (0x000001d8) > +#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG (0x000001dc) > + > +#define BP_ANADIG_USB1_CHRG_DET_STAT_RSVD0 4 > +#define BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 > +#define BF_ANADIG_USB1_CHRG_DET_STAT_RSVD0(v) \ > + (((v) << 4) & BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0) > +#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008 > +#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004 > +#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 > +#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 > + > +#define HW_ANADIG_USB1_LOOPBACK (0x000001e0) > +#define HW_ANADIG_USB1_LOOPBACK_SET (0x000001e4) > +#define HW_ANADIG_USB1_LOOPBACK_CLR (0x000001e8) > +#define HW_ANADIG_USB1_LOOPBACK_TOG (0x000001ec) > + > +#define BP_ANADIG_USB1_LOOPBACK_RSVD0 9 > +#define BM_ANADIG_USB1_LOOPBACK_RSVD0 0xFFFFFE00 > +#define BF_ANADIG_USB1_LOOPBACK_RSVD0(v) \ > + (((v) << 9) & BM_ANADIG_USB1_LOOPBACK_RSVD0) > +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100 > +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080 > +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040 > +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020 > +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 > +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 > +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004 > +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002 > +#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001 > + > +#define HW_ANADIG_USB1_MISC (0x000001f0) > +#define HW_ANADIG_USB1_MISC_SET (0x000001f4) > +#define HW_ANADIG_USB1_MISC_CLR (0x000001f8) > +#define HW_ANADIG_USB1_MISC_TOG (0x000001fc) > + > +#define BM_ANADIG_USB1_MISC_RSVD1 0x80000000 > +#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000 > +#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000 > +#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000 > +#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000 > +#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000 > +#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000 > +#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000 > +#define BP_ANADIG_USB1_MISC_RSVD0 2 > +#define BM_ANADIG_USB1_MISC_RSVD0 0x00FFFFFC > +#define BF_ANADIG_USB1_MISC_RSVD0(v) \ > + (((v) << 2) & BM_ANADIG_USB1_MISC_RSVD0) > +#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002 > +#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001 > + > +#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200) > +#define HW_ANADIG_USB2_VBUS_DETECT_SET (0x00000204) > +#define HW_ANADIG_USB2_VBUS_DETECT_CLR (0x00000208) > +#define HW_ANADIG_USB2_VBUS_DETECT_TOG (0x0000020c) > + > +#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 > +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD2 28 > +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD2 0x70000000 > +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD2(v) \ > + (((v) << 28) & BM_ANADIG_USB2_VBUS_DETECT_RSVD2) > +#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000 > +#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 > +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD1 21 > +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD1 0x03E00000 > +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD1(v) \ > + (((v) << 21) & BM_ANADIG_USB2_VBUS_DETECT_RSVD1) > +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 > +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 > +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 > +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD0 3 > +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD0 0x0003FFF8 > +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD0(v) \ > + (((v) << 3) & BM_ANADIG_USB2_VBUS_DETECT_RSVD0) > +#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0 > +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 > +#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) \ > + (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH) > + > +#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) > +#define HW_ANADIG_USB2_CHRG_DETECT_SET (0x00000214) > +#define HW_ANADIG_USB2_CHRG_DETECT_CLR (0x00000218) > +#define HW_ANADIG_USB2_CHRG_DETECT_TOG (0x0000021c) > + > +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD2 24 > +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD2 0xFF000000 > +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD2(v) \ > + (((v) << 24) & BM_ANADIG_USB2_CHRG_DETECT_RSVD2) > +#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000 > +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD1 21 > +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD1 0x00600000 > +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD1(v) \ > + (((v) << 21) & BM_ANADIG_USB2_CHRG_DETECT_RSVD1) > +#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 > +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 > +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000 > +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD0 1 > +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD0 0x0003FFFE > +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD0(v) \ > + (((v) << 1) & BM_ANADIG_USB2_CHRG_DETECT_RSVD0) > +#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001 > + > +#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220) > +#define HW_ANADIG_USB2_VBUS_DET_STAT_SET (0x00000224) > +#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR (0x00000228) > +#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG (0x0000022c) > + > +#define BP_ANADIG_USB2_VBUS_DET_STAT_RSVD0 4 > +#define BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 > +#define BF_ANADIG_USB2_VBUS_DET_STAT_RSVD0(v) \ > + (((v) << 4) & BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0) > +#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008 > +#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004 > +#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002 > +#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001 > + > +#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230) > +#define HW_ANADIG_USB2_CHRG_DET_STAT_SET (0x00000234) > +#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR (0x00000238) > +#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG (0x0000023c) > + > +#define BP_ANADIG_USB2_CHRG_DET_STAT_RSVD0 4 > +#define BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 > +#define BF_ANADIG_USB2_CHRG_DET_STAT_RSVD0(v) \ > + (((v) << 4) & BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0) > +#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008 > +#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004 > +#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 > +#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 > + > +#define HW_ANADIG_USB2_LOOPBACK (0x00000240) > +#define HW_ANADIG_USB2_LOOPBACK_SET (0x00000244) > +#define HW_ANADIG_USB2_LOOPBACK_CLR (0x00000248) > +#define HW_ANADIG_USB2_LOOPBACK_TOG (0x0000024c) > + > +#define BP_ANADIG_USB2_LOOPBACK_RSVD0 9 > +#define BM_ANADIG_USB2_LOOPBACK_RSVD0 0xFFFFFE00 > +#define BF_ANADIG_USB2_LOOPBACK_RSVD0(v) \ > + (((v) << 9) & BM_ANADIG_USB2_LOOPBACK_RSVD0) > +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100 > +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080 > +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040 > +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020 > +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 > +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 > +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004 > +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002 > +#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001 > + > +#define HW_ANADIG_USB2_MISC (0x00000250) > +#define HW_ANADIG_USB2_MISC_SET (0x00000254) > +#define HW_ANADIG_USB2_MISC_CLR (0x00000258) > +#define HW_ANADIG_USB2_MISC_TOG (0x0000025c) > + > +#define BM_ANADIG_USB2_MISC_RSVD1 0x80000000 > +#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000 > +#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000 > +#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000 > +#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000 > +#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000 > +#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000 > +#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000 > +#define BP_ANADIG_USB2_MISC_RSVD0 2 > +#define BM_ANADIG_USB2_MISC_RSVD0 0x00FFFFFC > +#define BF_ANADIG_USB2_MISC_RSVD0(v) \ > + (((v) << 2) & BM_ANADIG_USB2_MISC_RSVD0) > +#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002 > +#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001 > + > +#define HW_ANADIG_DIGPROG (0x00000260) > + > +#define BP_ANADIG_DIGPROG_RSVD 24 > +#define BM_ANADIG_DIGPROG_RSVD 0xFF000000 > +#define BF_ANADIG_DIGPROG_RSVD(v) \ > + (((v) << 24) & BM_ANADIG_DIGPROG_RSVD) > +#define BP_ANADIG_DIGPROG_MAJOR 8 > +#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00 > +#define BF_ANADIG_DIGPROG_MAJOR(v) \ > + (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR) > +#define BP_ANADIG_DIGPROG_MINOR 0 > +#define BM_ANADIG_DIGPROG_MINOR 0x000000FF > +#define BF_ANADIG_DIGPROG_MINOR(v) \ > + (((v) << 0) & BM_ANADIG_DIGPROG_MINOR) > + > #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ > diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h > index 2631beb..4b44095 100644 > --- a/arch/arm/include/asm/arch-mx6/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h > @@ -1,5 +1,5 @@ > /* > - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. > + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. > * > * SPDX-License-Identifier: GPL-2.0+ > */ > @@ -587,6 +587,12 @@ struct fuse_bank0_regs { > u32 rsvd7[4]; > }; > > +struct fuse_bank1_regs { > + u32 mem[0x18]; > + u32 ana1; > + u32 ana2; > +}; > + > #ifdef CONFIG_MX6SX > struct fuse_bank4_regs { > u32 sjc_resp_low; > @@ -805,5 +811,6 @@ struct pwm_regs { > u32 pr; > u32 cnr; > }; > +void check_cpu_temperature(void); > #endif /* __ASSEMBLER__*/ > #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ > Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de ===================================================================== ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support 2014-09-11 9:01 ` Stefano Babic @ 2014-09-16 18:43 ` Nitin Garg 0 siblings, 0 replies; 5+ messages in thread From: Nitin Garg @ 2014-09-16 18:43 UTC (permalink / raw) To: u-boot Hi Stefano, On 09/11/2014 04:01 AM, Stefano Babic wrote: > Hi Nitin, > > > On 02/09/2014 00:48, nitin.garg at freescale.com wrote: >> From: Nitin Garg <nitin.garg@freescale.com> >> >> i.MX6 SoC has onChip temperature sensor. Add support >> for this sensor. >> >> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> >> --- >> arch/arm/cpu/armv7/mx6/soc.c | 138 +++++++- >> arch/arm/imx-common/cpu.c | 7 +- >> arch/arm/include/asm/arch-mx6/crm_regs.h | 543 +++++++++++++++++++++++++++++- >> arch/arm/include/asm/arch-mx6/imx-regs.h | 9 +- >> 4 files changed, 693 insertions(+), 4 deletions(-) >> > > I tend to consider this as a driver instead of a couple of functions to > read/check temperature. Hiding this code inside cpu code does not get an > overview about which API is used. If another SOC (not necessarily > Freescale) will add such kind of functionality, we will have probably a > different API. > > I would prefer, without reinventing the wheel, to follow the kernel > approach and move this code into a driver, let's say into > drivers/thermal. Feel free to add this directory to u-boot tree. A name > as imx-thermal as in kernel looks to me appropriate for your code. Accepted. Reworked in v4. > >> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c >> index ac84a1f..b0c1306 100644 >> --- a/arch/arm/cpu/armv7/mx6/soc.c >> +++ b/arch/arm/cpu/armv7/mx6/soc.c >> @@ -2,7 +2,7 @@ >> * (C) Copyright 2007 >> * Sascha Hauer, Pengutronix >> * >> - * (C) Copyright 2009 Freescale Semiconductor, Inc. >> + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. >> * >> * SPDX-License-Identifier: GPL-2.0+ >> */ >> @@ -35,6 +35,16 @@ struct scu_regs { >> u32 fpga_rev; >> }; >> >> +#define TEMPERATURE_MIN -40 >> +#define TEMPERATURE_HOT 80 >> +#define TEMPERATURE_MAX 125 >> +#define FACTOR1 15976 >> +#define FACTOR2 4297157 >> +#define MEASURE_FREQ 327 >> + >> +#define REG_VALUE_TO_CEL(ratio, raw) \ >> + ((raw_n40c - raw) * 100 / ratio - 40) >> + >> u32 get_nr_cpus(void) >> { >> struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; >> @@ -218,6 +228,132 @@ static void imx_set_wdog_powerdown(bool enable) >> writew(enable, &wdog2->wmcr); >> } >> >> +#ifdef CONFIG_IMX6_TEMP_SENSOR > > TEMP is rather a misleading name. It can be confused with temporary. > Maybe CONFIG_IMX_THERMAL or CONFIG_IMX_THERMAL_SENSOR ? > Accepted. Reworked in v4. >> +static int read_cpu_temperature(u32 *fuse) >> +{ >> + int temperature; >> + unsigned int ccm_ccgr2; >> + unsigned int reg, tmp; >> + unsigned int raw_25c, raw_n40c, ratio; >> + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; >> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; >> + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; >> + struct fuse_bank *bank = &ocotp->bank[1]; >> + struct fuse_bank1_regs *fuse_bank1 = >> + (struct fuse_bank1_regs *)bank->fuse_regs; >> + >> + /* need to make sure pll3 is enabled for thermal sensor */ > > The code to enable a clock should go into armv7/mx6/clock.c. > Accepted. Reworked in v4. >> + if ((readl(&anatop->usb1_pll_480_ctrl) & >> + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) { >> + /* enable pll's power */ >> + writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER, >> + &anatop->usb1_pll_480_ctrl_set); >> + writel(0x80, &anatop->ana_misc2_clr); >> + /* wait for pll lock */ >> + while ((readl(&anatop->usb1_pll_480_ctrl) & >> + BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) >> + ; >> + /* disable bypass */ >> + writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS, >> + &anatop->usb1_pll_480_ctrl_clr); >> + /* enable pll output */ >> + writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE, >> + &anatop->usb1_pll_480_ctrl_set); >> + } >> + >> + ccm_ccgr2 = readl(&mxc_ccm->CCGR2); >> + /* enable OCOTP_CTRL clock in CCGR2 */ >> + writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, &mxc_ccm->CCGR2); > > You are readding the same code we have already merged. We have a ocotp > driver in u-boot, and this uses enable_ocotp_clk() to enable and disable > the clock. Please use also the functions provide by the ocotp driver. I > suggest you add a Kconfig rule to make this driver dependend on ocotp. > Since OCOTP in not in Kconfig (instead in header), I have added a rule in config header to enable OCOTP when IMX6_THERMAL is enabled. Pls accept. >> + *fuse = readl(&fuse_bank1->ana1); >> + >> + /* restore CCGR2 */ >> + writel(ccm_ccgr2, &mxc_ccm->CCGR2); >> + >> + if (*fuse == 0 || *fuse == 0xffffffff || (*fuse & 0xfff00000) == 0) >> + return TEMPERATURE_MIN; >> + > > Does it mean invalid values ? According to manual, the register is split > into three different regions (Room, Hot_count, Hot_temp) and I am > wondering we can simply compare the whole register. If your check means > that you are reading invalid or not expected values, an error should be > reported instead of falling back to the minimal temperature. > Accepted. Reworked in v4. >> + /* >> + * fuse data layout: >> + * [31:20] sensor value @ 25C >> + * [19:8] sensor value of hot >> + * [7:0] hot temperature value >> + */ >> + raw_25c = *fuse >> 20; >> + >> + /* >> + * The universal equation for thermal sensor >> + * is slope = 0.4297157 - (0.0015976 * 25C fuse), >> + * here we convert them to integer to make them >> + * easy for counting, FACTOR1 is 15976, >> + * FACTOR2 is 4297157. Our ratio = -100 * slope > > You do not need you repeat the values for FACTORx in comments - they can > be defined in the file. >> + */ >> + ratio = ((FACTOR1 * raw_25c - FACTOR2) + 50000) / 100000; > > I think it would be better you do as in kernel, where it is explained > which formulas are involved with FACTORx. You are making also an > implicit round up to next FACTOR0, that is not explained here. > Accepted. Reworked in v4. Its now aligned to kernel. >> + >> + debug("Thermal sensor with ratio = %d\n", ratio); >> + >> + raw_n40c = raw_25c + (13 * ratio) / 20; > > Where are coming 13 and 20 ? > > Is there any reason why this computation is slightly different as in > linux kernel ? If it is possible, it will be better to stick with the > kernel implementation, allowing us in future an easier porting of fixes > from the kernel. And add in your commit message which is your kernel > version where you get the code (better with a commit-id). > Accepted. Reworked in v4. Its now aligned to kernel. >> + >> + /* >> + * now we only use single measure, every time we read >> + * the temperature, we will power on/down anadig thermal >> + * module >> + */ >> + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); >> + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); >> + >> + /* write measure freq */ >> + reg = readl(&anatop->tempsense1); >> + reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ; >> + reg |= MEASURE_FREQ; >> + writel(reg, &anatop->tempsense1); >> + >> + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); >> + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); >> + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); >> + >> + while ((readl(&anatop->tempsense0) & >> + BM_ANADIG_TEMPSENSE0_FINISHED) == 0) >> + udelay(10000); >> + >> + reg = readl(&anatop->tempsense0); >> + tmp = (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >> + >> BP_ANADIG_TEMPSENSE0_TEMP_VALUE; >> + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); >> + >> + if (tmp <= raw_n40c) >> + temperature = REG_VALUE_TO_CEL(ratio, tmp); >> + else >> + temperature = TEMPERATURE_MIN; >> + /* power down anatop thermal sensor */ >> + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); >> + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); >> + >> + return temperature; >> +} >> + >> +void check_cpu_temperature(void) >> +{ >> + int cpu_tmp = 0; >> + u32 fuse = ~0; >> + >> + cpu_tmp = read_cpu_temperature(&fuse); >> + while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) { >> + if (cpu_tmp >= TEMPERATURE_HOT) { >> + printf("CPU is %d C, too hot to boot, waiting...\n", >> + cpu_tmp); >> + udelay(5000000); >> + cpu_tmp = read_cpu_temperature(&fuse); >> + } else { >> + break; >> + } > > I am asking myself if there are good reasons why the temperature will go > down. Should we not call hang() here ? Or does the cpu become colder in > this loop, then calling simply udelay ? > Yes, udelay helps cool down cpu. >> + } >> + if (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) >> + printf("CPU: Temperature %d C\n", cpu_tmp); >> + else >> + printf("CPU: Temperature: invalid data, fuse: 0x%x\n", fuse); >> +} >> +#endif >> + >> static void set_ahb_rate(u32 val) >> { >> struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; >> diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c >> index ed826a0..7253d37 100644 >> --- a/arch/arm/imx-common/cpu.c >> +++ b/arch/arm/imx-common/cpu.c >> @@ -2,7 +2,7 @@ >> * (C) Copyright 2007 >> * Sascha Hauer, Pengutronix >> * >> - * (C) Copyright 2009 Freescale Semiconductor, Inc. >> + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc. >> * >> * SPDX-License-Identifier: GPL-2.0+ >> */ >> @@ -139,6 +139,11 @@ int print_cpuinfo(void) >> (cpurev & 0x000F0) >> 4, >> (cpurev & 0x0000F) >> 0, >> mxc_get_clock(MXC_ARM_CLK) / 1000000); >> + >> +#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_TEMP_SENSOR) >> + check_cpu_temperature(); >> +#endif >> + >> printf("Reset cause: %s\n", get_reset_cause()); >> return 0; >> } >> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h >> index e67b5b9..66a7cea 100644 >> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h >> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h >> @@ -1,5 +1,5 @@ >> /* >> - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. >> + * Copyright 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. >> * >> * SPDX-License-Identifier: GPL-2.0+ >> */ >> @@ -1061,4 +1061,545 @@ struct mxc_ccm_reg { >> #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ >> (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) >> >> +#define HW_ANADIG_REG_1P1 (0x00000110) >> +#define HW_ANADIG_REG_1P1_SET (0x00000114) >> +#define HW_ANADIG_REG_1P1_CLR (0x00000118) >> +#define HW_ANADIG_REG_1P1_TOG (0x0000011c) >> + >> +#define BP_ANADIG_REG_1P1_RSVD2 18 >> +#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC0000 >> +#define BF_ANADIG_REG_1P1_RSVD2(v) \ >> + (((v) << 18) & BM_ANADIG_REG_1P1_RSVD2) >> +#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x00020000 >> +#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x00010000 >> +#define BP_ANADIG_REG_1P1_RSVD1 13 >> +#define BM_ANADIG_REG_1P1_RSVD1 0x0000E000 >> +#define BF_ANADIG_REG_1P1_RSVD1(v) \ >> + (((v) << 13) & BM_ANADIG_REG_1P1_RSVD1) >> +#define BP_ANADIG_REG_1P1_OUTPUT_TRG 8 >> +#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x00001F00 >> +#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v) \ >> + (((v) << 8) & BM_ANADIG_REG_1P1_OUTPUT_TRG) >> +#define BM_ANADIG_REG_1P1_RSVD0 0x00000080 >> +#define BP_ANADIG_REG_1P1_BO_OFFSET 4 >> +#define BM_ANADIG_REG_1P1_BO_OFFSET 0x00000070 >> +#define BF_ANADIG_REG_1P1_BO_OFFSET(v) \ >> + (((v) << 4) & BM_ANADIG_REG_1P1_BO_OFFSET) >> +#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x00000008 >> +#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x00000004 >> +#define BM_ANADIG_REG_1P1_ENABLE_BO 0x00000002 >> +#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x00000001 >> + >> +#define HW_ANADIG_REG_3P0 (0x00000120) >> +#define HW_ANADIG_REG_3P0_SET (0x00000124) >> +#define HW_ANADIG_REG_3P0_CLR (0x00000128) >> +#define HW_ANADIG_REG_3P0_TOG (0x0000012c) >> + >> +#define BP_ANADIG_REG_3P0_RSVD2 18 >> +#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC0000 >> +#define BF_ANADIG_REG_3P0_RSVD2(v) \ >> + (((v) << 18) & BM_ANADIG_REG_3P0_RSVD2) >> +#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x00020000 >> +#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x00010000 >> +#define BP_ANADIG_REG_3P0_RSVD1 13 >> +#define BM_ANADIG_REG_3P0_RSVD1 0x0000E000 >> +#define BF_ANADIG_REG_3P0_RSVD1(v) \ >> + (((v) << 13) & BM_ANADIG_REG_3P0_RSVD1) >> +#define BP_ANADIG_REG_3P0_OUTPUT_TRG 8 >> +#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x00001F00 >> +#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v) \ >> + (((v) << 8) & BM_ANADIG_REG_3P0_OUTPUT_TRG) >> +#define BM_ANADIG_REG_3P0_VBUS_SEL 0x00000080 >> +#define BP_ANADIG_REG_3P0_BO_OFFSET 4 >> +#define BM_ANADIG_REG_3P0_BO_OFFSET 0x00000070 >> +#define BF_ANADIG_REG_3P0_BO_OFFSET(v) \ >> + (((v) << 4) & BM_ANADIG_REG_3P0_BO_OFFSET) >> +#define BM_ANADIG_REG_3P0_RSVD0 0x00000008 >> +#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x00000004 >> +#define BM_ANADIG_REG_3P0_ENABLE_BO 0x00000002 >> +#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x00000001 >> + >> +#define HW_ANADIG_REG_2P5 (0x00000130) >> +#define HW_ANADIG_REG_2P5_SET (0x00000134) >> +#define HW_ANADIG_REG_2P5_CLR (0x00000138) >> +#define HW_ANADIG_REG_2P5_TOG (0x0000013c) >> + >> +#define BP_ANADIG_REG_2P5_RSVD2 19 >> +#define BM_ANADIG_REG_2P5_RSVD2 0xFFF80000 >> +#define BF_ANADIG_REG_2P5_RSVD2(v) \ >> + (((v) << 19) & BM_ANADIG_REG_2P5_RSVD2) >> +#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x00040000 >> +#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x00020000 >> +#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x00010000 >> +#define BP_ANADIG_REG_2P5_RSVD1 13 >> +#define BM_ANADIG_REG_2P5_RSVD1 0x0000E000 >> +#define BF_ANADIG_REG_2P5_RSVD1(v) \ >> + (((v) << 13) & BM_ANADIG_REG_2P5_RSVD1) >> +#define BP_ANADIG_REG_2P5_OUTPUT_TRG 8 >> +#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x00001F00 >> +#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v) \ >> + (((v) << 8) & BM_ANADIG_REG_2P5_OUTPUT_TRG) >> +#define BM_ANADIG_REG_2P5_RSVD0 0x00000080 >> +#define BP_ANADIG_REG_2P5_BO_OFFSET 4 >> +#define BM_ANADIG_REG_2P5_BO_OFFSET 0x00000070 >> +#define BF_ANADIG_REG_2P5_BO_OFFSET(v) \ >> + (((v) << 4) & BM_ANADIG_REG_2P5_BO_OFFSET) >> +#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x00000008 >> +#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x00000004 >> +#define BM_ANADIG_REG_2P5_ENABLE_BO 0x00000002 >> +#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x00000001 >> + >> +#define HW_ANADIG_REG_CORE (0x00000140) >> +#define HW_ANADIG_REG_CORE_SET (0x00000144) >> +#define HW_ANADIG_REG_CORE_CLR (0x00000148) >> +#define HW_ANADIG_REG_CORE_TOG (0x0000014c) >> + >> +#define BM_ANADIG_REG_CORE_REF_SHIFT 0x80000000 >> +#define BM_ANADIG_REG_CORE_RSVD0 0x40000000 >> +#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000 >> +#define BP_ANADIG_REG_CORE_RAMP_RATE 27 >> +#define BM_ANADIG_REG_CORE_RAMP_RATE 0x18000000 >> +#define BF_ANADIG_REG_CORE_RAMP_RATE(v) \ >> + (((v) << 27) & BM_ANADIG_REG_CORE_RAMP_RATE) >> +#define BP_ANADIG_REG_CORE_REG2_ADJ 23 >> +#define BM_ANADIG_REG_CORE_REG2_ADJ 0x07800000 >> +#define BF_ANADIG_REG_CORE_REG2_ADJ(v) \ >> + (((v) << 23) & BM_ANADIG_REG_CORE_REG2_ADJ) >> +#define BP_ANADIG_REG_CORE_REG2_TRG 18 >> +#define BM_ANADIG_REG_CORE_REG2_TRG 0x007C0000 >> +#define BF_ANADIG_REG_CORE_REG2_TRG(v) \ >> + (((v) << 18) & BM_ANADIG_REG_CORE_REG2_TRG) >> +#define BP_ANADIG_REG_CORE_REG1_ADJ 14 >> +#define BM_ANADIG_REG_CORE_REG1_ADJ 0x0003C000 >> +#define BF_ANADIG_REG_CORE_REG1_ADJ(v) \ >> + (((v) << 14) & BM_ANADIG_REG_CORE_REG1_ADJ) >> +#define BP_ANADIG_REG_CORE_REG1_TRG 9 >> +#define BM_ANADIG_REG_CORE_REG1_TRG 0x00003E00 >> +#define BF_ANADIG_REG_CORE_REG1_TRG(v) \ >> + (((v) << 9) & BM_ANADIG_REG_CORE_REG1_TRG) >> +#define BP_ANADIG_REG_CORE_REG0_ADJ 5 >> +#define BM_ANADIG_REG_CORE_REG0_ADJ 0x000001E0 >> +#define BF_ANADIG_REG_CORE_REG0_ADJ(v) \ >> + (((v) << 5) & BM_ANADIG_REG_CORE_REG0_ADJ) >> +#define BP_ANADIG_REG_CORE_REG0_TRG 0 >> +#define BM_ANADIG_REG_CORE_REG0_TRG 0x0000001F >> +#define BF_ANADIG_REG_CORE_REG0_TRG(v) \ >> + (((v) << 0) & BM_ANADIG_REG_CORE_REG0_TRG) >> + >> +#define HW_ANADIG_ANA_MISC0 (0x00000150) >> +#define HW_ANADIG_ANA_MISC0_SET (0x00000154) >> +#define HW_ANADIG_ANA_MISC0_CLR (0x00000158) >> +#define HW_ANADIG_ANA_MISC0_TOG (0x0000015c) >> + >> +#define BP_ANADIG_ANA_MISC0_RSVD2 29 >> +#define BM_ANADIG_ANA_MISC0_RSVD2 0xE0000000 >> +#define BF_ANADIG_ANA_MISC0_RSVD2(v) \ >> + (((v) << 29) & BM_ANADIG_ANA_MISC0_RSVD2) >> +#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 >> +#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY 0x1C000000 >> +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ >> + (((v) << 26) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) >> +#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL 0x02000000 >> +#define BP_ANADIG_ANA_MISC0_ANAMUX 21 >> +#define BM_ANADIG_ANA_MISC0_ANAMUX 0x01E00000 >> +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ >> + (((v) << 21) & BM_ANADIG_ANA_MISC0_ANAMUX) >> +#define BM_ANADIG_ANA_MISC0_ANAMUX_EN 0x00100000 >> +#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 >> +#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 0x000C0000 >> +#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ >> + (((v) << 18) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) >> +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN 0x00020000 >> +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK 0x00010000 >> +#define BP_ANADIG_ANA_MISC0_OSC_I 14 >> +#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 >> +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ >> + (((v) << 14) & BM_ANADIG_ANA_MISC0_OSC_I) >> +#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN 0x00002000 >> +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x00001000 >> +#define BP_ANADIG_ANA_MISC0_RSVD0 10 >> +#define BM_ANADIG_ANA_MISC0_RSVD0 0x00000C00 >> +#define BF_ANADIG_ANA_MISC0_RSVD0(v) \ >> + (((v) << 10) & BM_ANADIG_ANA_MISC0_RSVD0) >> +#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 >> +#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 >> +#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \ >> + (((v) << 8) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) >> +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP 0x00000080 >> +#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 >> +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x00000070 >> +#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ >> + (((v) << 4) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) >> +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 >> +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER 0x00000004 >> +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP 0x00000002 >> +#define BM_ANADIG_ANA_MISC0_REFTOP_PWD 0x00000001 >> + >> +#define HW_ANADIG_ANA_MISC1 (0x00000160) >> +#define HW_ANADIG_ANA_MISC1_SET (0x00000164) >> +#define HW_ANADIG_ANA_MISC1_CLR (0x00000168) >> +#define HW_ANADIG_ANA_MISC1_TOG (0x0000016c) >> + >> +#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO 0x80000000 >> +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 >> +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 >> +#define BP_ANADIG_ANA_MISC1_RSVD0 14 >> +#define BM_ANADIG_ANA_MISC1_RSVD0 0x1FFFC000 >> +#define BF_ANADIG_ANA_MISC1_RSVD0(v) \ >> + (((v) << 14) & BM_ANADIG_ANA_MISC1_RSVD0) >> +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN 0x00002000 >> +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN 0x00001000 >> +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN 0x00000800 >> +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN 0x00000400 >> +#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 >> +#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 >> +#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ >> + (((v) << 5) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) >> +#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 >> +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F >> +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ >> + (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) >> + >> +#define HW_ANADIG_ANA_MISC2 (0x00000170) >> +#define HW_ANADIG_ANA_MISC2_SET (0x00000174) >> +#define HW_ANADIG_ANA_MISC2_CLR (0x00000178) >> +#define HW_ANADIG_ANA_MISC2_TOG (0x0000017c) >> + >> +#define BP_ANADIG_ANA_MISC2_CONTROL3 30 >> +#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 >> +#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ >> + (((v) << 30) & BM_ANADIG_ANA_MISC2_CONTROL3) >> +#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 >> +#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 >> +#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ >> + (((v) << 28) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) >> +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 >> +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 >> +#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ >> + (((v) << 26) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) >> +#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 >> +#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 >> +#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ >> + (((v) << 24) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) >> +#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 >> +#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 >> +#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO 0x00200000 >> +#define BM_ANADIG_ANA_MISC2_RSVD2 0x00100000 >> +#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS 0x00080000 >> +#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 >> +#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 >> +#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ >> + (((v) << 16) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) >> +#define BM_ANADIG_ANA_MISC2_CONTROL1 0x00008000 >> +#define BM_ANADIG_ANA_MISC2_REG1_OK 0x00004000 >> +#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO 0x00002000 >> +#define BM_ANADIG_ANA_MISC2_RSVD1 0x00001000 >> +#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS 0x00000800 >> +#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 >> +#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 >> +#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ >> + (((v) << 8) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) >> +#define BM_ANADIG_ANA_MISC2_CONTROL0 0x00000080 >> +#define BM_ANADIG_ANA_MISC2_REG0_OK 0x00000040 >> +#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO 0x00000020 >> +#define BM_ANADIG_ANA_MISC2_RSVD0 0x00000010 >> +#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS 0x00000008 >> +#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 >> +#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0x00000007 >> +#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ >> + (((v) << 0) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) >> + >> +#define HW_ANADIG_TEMPSENSE0 (0x00000180) >> +#define HW_ANADIG_TEMPSENSE0_SET (0x00000184) >> +#define HW_ANADIG_TEMPSENSE0_CLR (0x00000188) >> +#define HW_ANADIG_TEMPSENSE0_TOG (0x0000018c) >> + >> +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 >> +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE 0xFFF00000 >> +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ >> + (((v) << 20) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) >> +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 >> +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE 0x000FFF00 >> +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ >> + (((v) << 8) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >> +#define BM_ANADIG_TEMPSENSE0_RSVD0 0x00000080 >> +#define BM_ANADIG_TEMPSENSE0_TEST 0x00000040 >> +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 >> +#define BM_ANADIG_TEMPSENSE0_VBGADJ 0x00000038 >> +#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ >> + (((v) << 3) & BM_ANADIG_TEMPSENSE0_VBGADJ) >> +#define BM_ANADIG_TEMPSENSE0_FINISHED 0x00000004 >> +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP 0x00000002 >> +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN 0x00000001 >> + >> +#define HW_ANADIG_TEMPSENSE1 (0x00000190) >> +#define HW_ANADIG_TEMPSENSE1_SET (0x00000194) >> +#define HW_ANADIG_TEMPSENSE1_CLR (0x00000198) >> +#define HW_ANADIG_TEMPSENSE1_TOG (0x0000019c) >> + >> +#define BP_ANADIG_TEMPSENSE1_RSVD0 16 >> +#define BM_ANADIG_TEMPSENSE1_RSVD0 0xFFFF0000 >> +#define BF_ANADIG_TEMPSENSE1_RSVD0(v) \ >> + (((v) << 16) & BM_ANADIG_TEMPSENSE1_RSVD0) >> +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 >> +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ 0x0000FFFF >> +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ >> + (((v) << 0) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) >> + >> +#define HW_ANADIG_USB1_VBUS_DETECT (0x000001a0) >> +#define HW_ANADIG_USB1_VBUS_DETECT_SET (0x000001a4) >> +#define HW_ANADIG_USB1_VBUS_DETECT_CLR (0x000001a8) >> +#define HW_ANADIG_USB1_VBUS_DETECT_TOG (0x000001ac) >> + >> +#define BM_ANADIG_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 >> +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD2 28 >> +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD2 0x70000000 >> +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD2(v) \ >> + (((v) << 28) & BM_ANADIG_USB1_VBUS_DETECT_RSVD2) >> +#define BM_ANADIG_USB1_VBUS_DETECT_CHARGE_VBUS 0x08000000 >> +#define BM_ANADIG_USB1_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 >> +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD1 21 >> +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD1 0x03E00000 >> +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD1(v) \ >> + (((v) << 21) & BM_ANADIG_USB1_VBUS_DETECT_RSVD1) >> +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 >> +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 >> +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 >> +#define BP_ANADIG_USB1_VBUS_DETECT_RSVD0 8 >> +#define BM_ANADIG_USB1_VBUS_DETECT_RSVD0 0x0003FF00 >> +#define BF_ANADIG_USB1_VBUS_DETECT_RSVD0(v) \ >> + (((v) << 8) & BM_ANADIG_USB1_VBUS_DETECT_RSVD0) >> +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE 0x00000080 >> +#define BM_ANADIG_USB1_VBUS_DETECT_AVALID_OVERRIDE 0x00000040 >> +#define BM_ANADIG_USB1_VBUS_DETECT_BVALID_OVERRIDE 0x00000020 >> +#define BM_ANADIG_USB1_VBUS_DETECT_SESSEND_OVERRIDE 0x00000010 >> +#define BM_ANADIG_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN 0x00000008 >> +#define BP_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0 >> +#define BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 >> +#define BF_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH(v) \ >> + (((v) << 0) & BM_ANADIG_USB1_VBUS_DETECT_VBUSVALID_THRESH) >> + > > I disagree with these changes. You are adding a temperature sensors, and > we are waiting here all changes to make this sensor working. But I see a > lot of changes related to USB, and they, if required, should be posted > in a separate patch explaining what they are fixing. > Accepted. Reworked in v4 and this is a separate commit now. >> +#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0) >> +#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4) >> +#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8) >> +#define HW_ANADIG_USB1_CHRG_DETECT_TOG (0x000001bc) >> + >> +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD2 24 >> +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD2 0xFF000000 >> +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD2(v) \ >> + (((v) << 24) & BM_ANADIG_USB1_CHRG_DETECT_RSVD2) >> +#define BM_ANADIG_USB1_CHRG_DETECT_BGR_BIAS 0x00800000 >> +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD1 21 >> +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD1 0x00600000 >> +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD1(v) \ >> + (((v) << 21) & BM_ANADIG_USB1_CHRG_DETECT_RSVD1) >> +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 >> +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 >> +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000 >> +#define BP_ANADIG_USB1_CHRG_DETECT_RSVD0 1 >> +#define BM_ANADIG_USB1_CHRG_DETECT_RSVD0 0x0003FFFE >> +#define BF_ANADIG_USB1_CHRG_DETECT_RSVD0(v) \ >> + (((v) << 1) & BM_ANADIG_USB1_CHRG_DETECT_RSVD0) >> +#define BM_ANADIG_USB1_CHRG_DETECT_FORCE_DETECT 0x00000001 >> + >> +#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0) >> +#define HW_ANADIG_USB1_VBUS_DET_STAT_SET (0x000001c4) >> +#define HW_ANADIG_USB1_VBUS_DET_STAT_CLR (0x000001c8) >> +#define HW_ANADIG_USB1_VBUS_DET_STAT_TOG (0x000001cc) >> + >> +#define BP_ANADIG_USB1_VBUS_DET_STAT_RSVD0 4 >> +#define BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 >> +#define BF_ANADIG_USB1_VBUS_DET_STAT_RSVD0(v) \ >> + (((v) << 4) & BM_ANADIG_USB1_VBUS_DET_STAT_RSVD0) >> +#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008 >> +#define BM_ANADIG_USB1_VBUS_DET_STAT_AVALID 0x00000004 >> +#define BM_ANADIG_USB1_VBUS_DET_STAT_BVALID 0x00000002 >> +#define BM_ANADIG_USB1_VBUS_DET_STAT_SESSEND 0x00000001 >> + >> +#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0) >> +#define HW_ANADIG_USB1_CHRG_DET_STAT_SET (0x000001d4) >> +#define HW_ANADIG_USB1_CHRG_DET_STAT_CLR (0x000001d8) >> +#define HW_ANADIG_USB1_CHRG_DET_STAT_TOG (0x000001dc) >> + >> +#define BP_ANADIG_USB1_CHRG_DET_STAT_RSVD0 4 >> +#define BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 >> +#define BF_ANADIG_USB1_CHRG_DET_STAT_RSVD0(v) \ >> + (((v) << 4) & BM_ANADIG_USB1_CHRG_DET_STAT_RSVD0) >> +#define BM_ANADIG_USB1_CHRG_DET_STAT_DP_STATE 0x00000008 >> +#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004 >> +#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 >> +#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 >> + >> +#define HW_ANADIG_USB1_LOOPBACK (0x000001e0) >> +#define HW_ANADIG_USB1_LOOPBACK_SET (0x000001e4) >> +#define HW_ANADIG_USB1_LOOPBACK_CLR (0x000001e8) >> +#define HW_ANADIG_USB1_LOOPBACK_TOG (0x000001ec) >> + >> +#define BP_ANADIG_USB1_LOOPBACK_RSVD0 9 >> +#define BM_ANADIG_USB1_LOOPBACK_RSVD0 0xFFFFFE00 >> +#define BF_ANADIG_USB1_LOOPBACK_RSVD0(v) \ >> + (((v) << 9) & BM_ANADIG_USB1_LOOPBACK_RSVD0) >> +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST1 0x00000100 >> +#define BM_ANADIG_USB1_LOOPBACK_UTMO_DIG_TST0 0x00000080 >> +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HIZ 0x00000040 >> +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN 0x00000020 >> +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 >> +#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 >> +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 0x00000004 >> +#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST0 0x00000002 >> +#define BM_ANADIG_USB1_LOOPBACK_UTMI_TESTSTART 0x00000001 >> + >> +#define HW_ANADIG_USB1_MISC (0x000001f0) >> +#define HW_ANADIG_USB1_MISC_SET (0x000001f4) >> +#define HW_ANADIG_USB1_MISC_CLR (0x000001f8) >> +#define HW_ANADIG_USB1_MISC_TOG (0x000001fc) >> + >> +#define BM_ANADIG_USB1_MISC_RSVD1 0x80000000 >> +#define BM_ANADIG_USB1_MISC_EN_CLK_UTMI 0x40000000 >> +#define BM_ANADIG_USB1_MISC_RX_VPIN_FS 0x20000000 >> +#define BM_ANADIG_USB1_MISC_RX_VMIN_FS 0x10000000 >> +#define BM_ANADIG_USB1_MISC_RX_RXD_FS 0x08000000 >> +#define BM_ANADIG_USB1_MISC_RX_SQUELCH 0x04000000 >> +#define BM_ANADIG_USB1_MISC_RX_DISCON_DET 0x02000000 >> +#define BM_ANADIG_USB1_MISC_RX_HS_DATA 0x01000000 >> +#define BP_ANADIG_USB1_MISC_RSVD0 2 >> +#define BM_ANADIG_USB1_MISC_RSVD0 0x00FFFFFC >> +#define BF_ANADIG_USB1_MISC_RSVD0(v) \ >> + (((v) << 2) & BM_ANADIG_USB1_MISC_RSVD0) >> +#define BM_ANADIG_USB1_MISC_EN_DEGLITCH 0x00000002 >> +#define BM_ANADIG_USB1_MISC_HS_USE_EXTERNAL_R 0x00000001 >> + >> +#define HW_ANADIG_USB2_VBUS_DETECT (0x00000200) >> +#define HW_ANADIG_USB2_VBUS_DETECT_SET (0x00000204) >> +#define HW_ANADIG_USB2_VBUS_DETECT_CLR (0x00000208) >> +#define HW_ANADIG_USB2_VBUS_DETECT_TOG (0x0000020c) >> + >> +#define BM_ANADIG_USB2_VBUS_DETECT_EN_CHARGER_RESISTOR 0x80000000 >> +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD2 28 >> +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD2 0x70000000 >> +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD2(v) \ >> + (((v) << 28) & BM_ANADIG_USB2_VBUS_DETECT_RSVD2) >> +#define BM_ANADIG_USB2_VBUS_DETECT_CHARGE_VBUS 0x08000000 >> +#define BM_ANADIG_USB2_VBUS_DETECT_DISCHARGE_VBUS 0x04000000 >> +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD1 21 >> +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD1 0x03E00000 >> +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD1(v) \ >> + (((v) << 21) & BM_ANADIG_USB2_VBUS_DETECT_RSVD1) >> +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_PWRUP_CMPS 0x00100000 >> +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_5VDETECT 0x00080000 >> +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_TO_B 0x00040000 >> +#define BP_ANADIG_USB2_VBUS_DETECT_RSVD0 3 >> +#define BM_ANADIG_USB2_VBUS_DETECT_RSVD0 0x0003FFF8 >> +#define BF_ANADIG_USB2_VBUS_DETECT_RSVD0(v) \ >> + (((v) << 3) & BM_ANADIG_USB2_VBUS_DETECT_RSVD0) >> +#define BP_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0 >> +#define BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH 0x00000007 >> +#define BF_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH(v) \ >> + (((v) << 0) & BM_ANADIG_USB2_VBUS_DETECT_VBUSVALID_THRESH) >> + >> +#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) >> +#define HW_ANADIG_USB2_CHRG_DETECT_SET (0x00000214) >> +#define HW_ANADIG_USB2_CHRG_DETECT_CLR (0x00000218) >> +#define HW_ANADIG_USB2_CHRG_DETECT_TOG (0x0000021c) >> + >> +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD2 24 >> +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD2 0xFF000000 >> +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD2(v) \ >> + (((v) << 24) & BM_ANADIG_USB2_CHRG_DETECT_RSVD2) >> +#define BM_ANADIG_USB2_CHRG_DETECT_BGR_BIAS 0x00800000 >> +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD1 21 >> +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD1 0x00600000 >> +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD1(v) \ >> + (((v) << 21) & BM_ANADIG_USB2_CHRG_DETECT_RSVD1) >> +#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 >> +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 >> +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CONTACT 0x00040000 >> +#define BP_ANADIG_USB2_CHRG_DETECT_RSVD0 1 >> +#define BM_ANADIG_USB2_CHRG_DETECT_RSVD0 0x0003FFFE >> +#define BF_ANADIG_USB2_CHRG_DETECT_RSVD0(v) \ >> + (((v) << 1) & BM_ANADIG_USB2_CHRG_DETECT_RSVD0) >> +#define BM_ANADIG_USB2_CHRG_DETECT_FORCE_DETECT 0x00000001 >> + >> +#define HW_ANADIG_USB2_VBUS_DET_STAT (0x00000220) >> +#define HW_ANADIG_USB2_VBUS_DET_STAT_SET (0x00000224) >> +#define HW_ANADIG_USB2_VBUS_DET_STAT_CLR (0x00000228) >> +#define HW_ANADIG_USB2_VBUS_DET_STAT_TOG (0x0000022c) >> + >> +#define BP_ANADIG_USB2_VBUS_DET_STAT_RSVD0 4 >> +#define BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0 0xFFFFFFF0 >> +#define BF_ANADIG_USB2_VBUS_DET_STAT_RSVD0(v) \ >> + (((v) << 4) & BM_ANADIG_USB2_VBUS_DET_STAT_RSVD0) >> +#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID 0x00000008 >> +#define BM_ANADIG_USB2_VBUS_DET_STAT_AVALID 0x00000004 >> +#define BM_ANADIG_USB2_VBUS_DET_STAT_BVALID 0x00000002 >> +#define BM_ANADIG_USB2_VBUS_DET_STAT_SESSEND 0x00000001 >> + >> +#define HW_ANADIG_USB2_CHRG_DET_STAT (0x00000230) >> +#define HW_ANADIG_USB2_CHRG_DET_STAT_SET (0x00000234) >> +#define HW_ANADIG_USB2_CHRG_DET_STAT_CLR (0x00000238) >> +#define HW_ANADIG_USB2_CHRG_DET_STAT_TOG (0x0000023c) >> + >> +#define BP_ANADIG_USB2_CHRG_DET_STAT_RSVD0 4 >> +#define BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0 0xFFFFFFF0 >> +#define BF_ANADIG_USB2_CHRG_DET_STAT_RSVD0(v) \ >> + (((v) << 4) & BM_ANADIG_USB2_CHRG_DET_STAT_RSVD0) >> +#define BM_ANADIG_USB2_CHRG_DET_STAT_DP_STATE 0x00000008 >> +#define BM_ANADIG_USB2_CHRG_DET_STAT_DM_STATE 0x00000004 >> +#define BM_ANADIG_USB2_CHRG_DET_STAT_CHRG_DETECTED 0x00000002 >> +#define BM_ANADIG_USB2_CHRG_DET_STAT_PLUG_CONTACT 0x00000001 >> + >> +#define HW_ANADIG_USB2_LOOPBACK (0x00000240) >> +#define HW_ANADIG_USB2_LOOPBACK_SET (0x00000244) >> +#define HW_ANADIG_USB2_LOOPBACK_CLR (0x00000248) >> +#define HW_ANADIG_USB2_LOOPBACK_TOG (0x0000024c) >> + >> +#define BP_ANADIG_USB2_LOOPBACK_RSVD0 9 >> +#define BM_ANADIG_USB2_LOOPBACK_RSVD0 0xFFFFFE00 >> +#define BF_ANADIG_USB2_LOOPBACK_RSVD0(v) \ >> + (((v) << 9) & BM_ANADIG_USB2_LOOPBACK_RSVD0) >> +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST1 0x00000100 >> +#define BM_ANADIG_USB2_LOOPBACK_UTMO_DIG_TST0 0x00000080 >> +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HIZ 0x00000040 >> +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN 0x00000020 >> +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_LS_MODE 0x00000010 >> +#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_HS_MODE 0x00000008 >> +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 0x00000004 >> +#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST0 0x00000002 >> +#define BM_ANADIG_USB2_LOOPBACK_UTMI_TESTSTART 0x00000001 >> + >> +#define HW_ANADIG_USB2_MISC (0x00000250) >> +#define HW_ANADIG_USB2_MISC_SET (0x00000254) >> +#define HW_ANADIG_USB2_MISC_CLR (0x00000258) >> +#define HW_ANADIG_USB2_MISC_TOG (0x0000025c) >> + >> +#define BM_ANADIG_USB2_MISC_RSVD1 0x80000000 >> +#define BM_ANADIG_USB2_MISC_EN_CLK_UTMI 0x40000000 >> +#define BM_ANADIG_USB2_MISC_RX_VPIN_FS 0x20000000 >> +#define BM_ANADIG_USB2_MISC_RX_VMIN_FS 0x10000000 >> +#define BM_ANADIG_USB2_MISC_RX_RXD_FS 0x08000000 >> +#define BM_ANADIG_USB2_MISC_RX_SQUELCH 0x04000000 >> +#define BM_ANADIG_USB2_MISC_RX_DISCON_DET 0x02000000 >> +#define BM_ANADIG_USB2_MISC_RX_HS_DATA 0x01000000 >> +#define BP_ANADIG_USB2_MISC_RSVD0 2 >> +#define BM_ANADIG_USB2_MISC_RSVD0 0x00FFFFFC >> +#define BF_ANADIG_USB2_MISC_RSVD0(v) \ >> + (((v) << 2) & BM_ANADIG_USB2_MISC_RSVD0) >> +#define BM_ANADIG_USB2_MISC_EN_DEGLITCH 0x00000002 >> +#define BM_ANADIG_USB2_MISC_HS_USE_EXTERNAL_R 0x00000001 >> + >> +#define HW_ANADIG_DIGPROG (0x00000260) >> + >> +#define BP_ANADIG_DIGPROG_RSVD 24 >> +#define BM_ANADIG_DIGPROG_RSVD 0xFF000000 >> +#define BF_ANADIG_DIGPROG_RSVD(v) \ >> + (((v) << 24) & BM_ANADIG_DIGPROG_RSVD) >> +#define BP_ANADIG_DIGPROG_MAJOR 8 >> +#define BM_ANADIG_DIGPROG_MAJOR 0x00FFFF00 >> +#define BF_ANADIG_DIGPROG_MAJOR(v) \ >> + (((v) << 8) & BM_ANADIG_DIGPROG_MAJOR) >> +#define BP_ANADIG_DIGPROG_MINOR 0 >> +#define BM_ANADIG_DIGPROG_MINOR 0x000000FF >> +#define BF_ANADIG_DIGPROG_MINOR(v) \ >> + (((v) << 0) & BM_ANADIG_DIGPROG_MINOR) >> + >> #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ >> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h >> index 2631beb..4b44095 100644 >> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h >> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h >> @@ -1,5 +1,5 @@ >> /* >> - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. >> + * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved. >> * >> * SPDX-License-Identifier: GPL-2.0+ >> */ >> @@ -587,6 +587,12 @@ struct fuse_bank0_regs { >> u32 rsvd7[4]; >> }; >> >> +struct fuse_bank1_regs { >> + u32 mem[0x18]; >> + u32 ana1; >> + u32 ana2; >> +}; >> + >> #ifdef CONFIG_MX6SX >> struct fuse_bank4_regs { >> u32 sjc_resp_low; >> @@ -805,5 +811,6 @@ struct pwm_regs { >> u32 pr; >> u32 cnr; >> }; >> +void check_cpu_temperature(void); >> #endif /* __ASSEMBLER__*/ >> #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ >> > > Best regards, > Stefano Babic > Pls review v4. Regards, Nitin Garg ^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 2/2 v3] Enable SoC Temperature sensor for mx6 Sabre boards. 2014-09-01 22:48 [U-Boot] [PATCH 0/2 v3] Add support for mx6 onchip temperature sensor nitin.garg at freescale.com 2014-09-01 22:48 ` [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support nitin.garg at freescale.com @ 2014-09-01 22:48 ` nitin.garg at freescale.com 1 sibling, 0 replies; 5+ messages in thread From: nitin.garg at freescale.com @ 2014-09-01 22:48 UTC (permalink / raw) To: u-boot From: Nitin Garg <nitin.garg@freescale.com> Add CONFIG_IMX6_TEMP_SENSOR to mx6sabre_common.h file Signed-off-by: Nitin Garg <nitin.garg@freescale.com> --- include/configs/mx6sabre_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index e59a3b4..fc38ede 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -33,6 +33,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO +#define CONFIG_IMX6_TEMP_SENSOR #define CONFIG_MXC_UART -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2014-09-16 18:43 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-09-01 22:48 [U-Boot] [PATCH 0/2 v3] Add support for mx6 onchip temperature sensor nitin.garg at freescale.com 2014-09-01 22:48 ` [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support nitin.garg at freescale.com 2014-09-11 9:01 ` Stefano Babic 2014-09-16 18:43 ` Nitin Garg 2014-09-01 22:48 ` [U-Boot] [PATCH 2/2 v3] Enable SoC Temperature sensor for mx6 Sabre boards nitin.garg at freescale.com
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