Re: [PATCH] clk: rockchip: rk3288: add VOP1 softresets and rename VOP0 softresets

[mark <yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org>]

On 2014年09月12日 18:41, Heiko Stübner wrote:
> Hi Mark,
>
> Am Freitag, 12. September 2014, 18:33:23 schrieb Mark yao:
>> The rk3288 have two vop, and each vop has three softresets were axi_reset,
>> ahb_reset and dclk_reset.
> I'm not sure about renaming the indices, since they're part of the devicetree-
> binding. We know that so far no device in the wild used them, so it might be
> ok.
now vop driver need these reset, so we need add it.
> But in any case could you also add the rest of the indices of the "new" reset
> registers please, so that we don't end up adding each small index in a
> separate patch.
>
> patch1: add reset indices for SOFTRST9 - SOFTRST11
> patch2: rename LCDC0 -> VOP0
OK, I will do it
>
> Heiko
>
>> Signed-off-by: Mark yao <mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>>   include/dt-bindings/clock/rk3288-cru.h | 10 +++++++---
>>   1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/include/dt-bindings/clock/rk3288-cru.h
>> b/include/dt-bindings/clock/rk3288-cru.h index ebcb460..4d65959 100644
>> --- a/include/dt-bindings/clock/rk3288-cru.h
>> +++ b/include/dt-bindings/clock/rk3288-cru.h
>> @@ -235,9 +235,9 @@
>>   #define SRST_RGA_NIU		97
>>   #define SRST_VIO0_NIU_AXI	98
>>   #define SRST_VIO_NIU_AHB	99
>> -#define SRST_LCDC0_AXI		100
>> -#define SRST_LCDC0_AHB		101
>> -#define SRST_LCDC0_DCLK		102
>> +#define SRST_VOP0_AXI		100
>> +#define SRST_VOP0_AHB		101
>> +#define SRST_VOP0_DCLK		102
>>   #define SRST_VIO1_NIU_AXI	103
>>   #define SRST_VIP		104
>>   #define SRST_RGA_CORE		105
>> @@ -276,3 +276,7 @@
>>   #define SRST_USBHOST1_CON	140
>>   #define SRST_USB_ADP		141
>>   #define SRST_ACC_EFUSE		142
>> +
>> +#define SRST_VOP1_AXI		176
>> +#define SRST_VOP1_AHB		177
>> +#define SRST_VOP1_DCLK		178
>
>
>

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