[Qemu-devel] [PATCH 0/5] target-mips: Fix unused-function warnings

[Qemu-devel] [PATCH 0/5] target-mips: Fix unused-function warnings

[Peter Maydell]

These patches fix a number of warnings in target-mips code that
clang produces; notably, clang will complain about unused
'static inline' functions in .c files where gcc does not.
Some are genuinely totally unused; a few are unused only in some
configs and so we add ifdef guards.

(I've actually had these lying around for a while but forgot to
send them.)

Peter Maydell (5):
  target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX
  target-mips/translate.c: Add ifdef guard around check_mips64()
  target-mips/dsp_helper.c: Add ifdef guards around various functions
  target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()
  target-mips/op_helper.c: Remove unused do_lbu() function

 target-mips/dsp_helper.c | 26 ++++++++++++++++----------
 target-mips/op_helper.c  |  1 -
 target-mips/translate.c  | 22 +++-------------------
 3 files changed, 19 insertions(+), 30 deletions(-)

-- 
2.0.0

[Qemu-devel] [PATCH 1/5] target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX

[Peter Maydell]

Remove the functions gen_load_ACX and gen_store_ACX, which appear to have
been unused since they were first introduced many years ago. These functions
were the only places using the cpu_ACX[] array of TCG globals, so remove
that and its accompanying regnames_ACX[] as well.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-mips/translate.c | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 06db150..2ce9fed 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1012,7 +1012,7 @@ enum {
 /* global register indices */
 static TCGv_ptr cpu_env;
 static TCGv cpu_gpr[32], cpu_PC;
-static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC], cpu_ACX[MIPS_DSP_ACC];
+static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
 static TCGv cpu_dspctrl, btarget, bcond;
 static TCGv_i32 hflags;
 static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -1103,10 +1103,6 @@ static const char * const regnames_LO[] = {
     "LO0", "LO1", "LO2", "LO3",
 };
 
-static const char * const regnames_ACX[] = {
-    "ACX0", "ACX1", "ACX2", "ACX3",
-};
-
 static const char * const fregnames[] = {
     "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
     "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
@@ -1149,17 +1145,6 @@ static inline void gen_store_gpr (TCGv t, int reg)
         tcg_gen_mov_tl(cpu_gpr[reg], t);
 }
 
-/* Moves to/from ACX register.  */
-static inline void gen_load_ACX (TCGv t, int reg)
-{
-    tcg_gen_mov_tl(t, cpu_ACX[reg]);
-}
-
-static inline void gen_store_ACX (TCGv t, int reg)
-{
-    tcg_gen_mov_tl(cpu_ACX[reg], t);
-}
-
 /* Moves to/from shadow registers. */
 static inline void gen_load_srsgpr (int from, int to)
 {
@@ -15944,9 +15929,6 @@ void mips_tcg_init(void)
         cpu_LO[i] = tcg_global_mem_new(TCG_AREG0,
                                        offsetof(CPUMIPSState, active_tc.LO[i]),
                                        regnames_LO[i]);
-        cpu_ACX[i] = tcg_global_mem_new(TCG_AREG0,
-                                        offsetof(CPUMIPSState, active_tc.ACX[i]),
-                                        regnames_ACX[i]);
     }
     cpu_dspctrl = tcg_global_mem_new(TCG_AREG0,
                                      offsetof(CPUMIPSState, active_tc.DSPControl),
-- 
2.0.0

[Qemu-devel] [PATCH 2/5] target-mips/translate.c: Add ifdef guard around check_mips64()

[Peter Maydell]

The function check_mips64() is only used if TARGET_MIPS64 is defined;
add an ifdef guard to its definition to avoid warnings about it being
unused in other configurations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-mips/translate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 2ce9fed..b3a2a37 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1421,6 +1421,7 @@ static inline void check_insn(DisasContext *ctx, int flags)
     }
 }
 
+#ifdef TARGET_MIPS64
 /* This code generates a "reserved instruction" exception if 64-bit
    instructions are not enabled. */
 static inline void check_mips_64(DisasContext *ctx)
@@ -1428,6 +1429,7 @@ static inline void check_mips_64(DisasContext *ctx)
     if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
         generate_exception(ctx, EXCP_RI);
 }
+#endif
 
 /* Define small wrappers for gen_load_fpr* so that we have a uniform
    calling interface for 32 and 64-bit FPRs.  No sense in changing
-- 
2.0.0

[Qemu-devel] [PATCH 3/5] target-mips/dsp_helper.c: Add ifdef guards around various functions

[Peter Maydell]

Add ifdef TARGET_MIPS64 guards around various functions that are only
called from helpers for TARGET_MIPS64 CPUs; this avoids compiler
warnings when building other configs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-mips/dsp_helper.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 94083fb..09fb470 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -283,6 +283,7 @@ static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
     return result;
 }
 
+#ifdef TARGET_MIPS64
 /* a[0] is LO, a[1] is HI. */
 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
                                              int32_t ac,
@@ -336,6 +337,7 @@ static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
         set_DSPControl_overflow_flag(1, 16 + ac, env);
     }
 }
+#endif
 
 static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
                                           CPUMIPSState *env)
@@ -357,10 +359,12 @@ static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
     return a * b;
 }
 
+#ifdef TARGET_MIPS64
 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
 {
     return a * b;
 }
+#endif
 
 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
                                                 CPUMIPSState *env)
@@ -417,10 +421,12 @@ static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
     return a >> mov;
 }
 
+#ifdef TARGET_MIPS64
 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
 {
     return a >> mov;
 }
+#endif
 
 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
 {
@@ -479,6 +485,7 @@ static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
     return (temp >> 1) & 0x00FF;
 }
 
+#ifdef TARGET_MIPS64
 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
 {
     uint16_t temp;
@@ -496,6 +503,7 @@ static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
 
     return (temp >> 1) & 0x00FF;
 }
+#endif
 
 /*  128 bits long. p[0] is LO, p[1] is HI. */
 static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
@@ -511,6 +519,7 @@ static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
     p[1] = (acc >> 63) & 0x01;
 }
 
+#ifdef TARGET_MIPS64
 /* 128 bits long. p[0] is LO, p[1] is HI */
 static inline void mipsdsp_rashift_acc(uint64_t *p,
                                        uint32_t ac,
@@ -558,6 +567,7 @@ static inline void mipsdsp_rndrashift_acc(uint64_t *p,
         }
     }
 }
+#endif
 
 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
                                           CPUMIPSState *env)
@@ -608,10 +618,12 @@ static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
     return tempI & 0x0000FFFF;
 }
 
+#ifdef TARGET_MIPS64
 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
 {
     return (uint64_t)a * (uint64_t)b;
 }
+#endif
 
 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
                                                  CPUMIPSState *env)
@@ -717,7 +729,7 @@ static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
     return a << s;
 }
 
-
+#ifdef TARGET_MIPS64
 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
                                         CPUMIPSState *env)
 {
@@ -734,6 +746,7 @@ static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
         return a << s;
     }
 }
+#endif
 
 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
                                             CPUMIPSState *env)
@@ -973,6 +986,7 @@ static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
     return temp & 0x00FF;
 }
 
+#ifdef TARGET_MIPS64
 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
 {
     int32_t temp;
@@ -997,6 +1011,7 @@ static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
 
     return temp;
 }
+#endif
 
 static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
 {
-- 
2.0.0

[Qemu-devel] [PATCH 4/5] target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()

[Peter Maydell]

The function get_DSPControl_24() is unused; remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-mips/dsp_helper.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 09fb470..349f2a0 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -76,15 +76,6 @@ static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
   env->active_tc.DSPControl |= (target_ulong)flag << 24;
 }
 
-static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
-{
-  uint32_t filter;
-
-  filter = (0x01 << len) - 1;
-
-  return (env->active_tc.DSPControl >> 24) & filter;
-}
-
 static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
 {
     target_ulong dspc;
-- 
2.0.0

[Qemu-devel] [PATCH 5/5] target-mips/op_helper.c: Remove unused do_lbu() function

[Peter Maydell]

The do_lbu() function defined by the expansion of HELPER_LD() is
never used, so don't define it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-mips/op_helper.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index df97b35..66aedc1 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -90,7 +90,6 @@ static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
     }                                                                   \
 }
 #endif
-HELPER_LD(lbu, ldub, uint8_t)
 HELPER_LD(lw, ldl, int32_t)
 #ifdef TARGET_MIPS64
 HELPER_LD(ld, ldq, int64_t)
-- 
2.0.0

Re: [Qemu-devel] [PATCH 0/5] target-mips: Fix unused-function warnings

[Richard Henderson]

On 09/14/2014 12:45 PM, Peter Maydell wrote:
> These patches fix a number of warnings in target-mips code that
> clang produces; notably, clang will complain about unused
> 'static inline' functions in .c files where gcc does not.
> Some are genuinely totally unused; a few are unused only in some
> configs and so we add ifdef guards.
> 
> (I've actually had these lying around for a while but forgot to
> send them.)
> 
> Peter Maydell (5):
>   target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACX
>   target-mips/translate.c: Add ifdef guard around check_mips64()
>   target-mips/dsp_helper.c: Add ifdef guards around various functions
>   target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()
>   target-mips/op_helper.c: Remove unused do_lbu() function
> 
>  target-mips/dsp_helper.c | 26 ++++++++++++++++----------
>  target-mips/op_helper.c  |  1 -
>  target-mips/translate.c  | 22 +++-------------------
>  3 files changed, 19 insertions(+), 30 deletions(-)
> 

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~