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From: Jiang Liu <jiang.liu@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	"Rafael J. Wysocki" <rjw@rjwysocki.net>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	Yinghai Lu <yinghai@kernel.org>, Borislav Petkov <bp@alien8.de>,
	Grant Likely <grant.likely@linaro.org>,
	Marc Zyngier <marc.zyngier@arm.com>,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Tony Luck <tony.luck@intel.com>, Joerg Roedel <joro@8bytes.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC Part2 v1 03/21] x86, irq: Save destination CPU ID in irq_cfg
Date: Wed, 17 Sep 2014 10:24:59 +0800	[thread overview]
Message-ID: <5418F0FB.6090004@linux.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1409161046460.4247@nanos>



On 2014/9/17 1:47, Thomas Gleixner wrote:
> 
> 
> On Thu, 11 Sep 2014, Jiang Liu wrote:
> 
>> Cache destination CPU APIC ID into struct irq_cfg when assigning vector
>> for interrupt. Upper layer just needs to read the cached APIC ID instead
>> of calling apic->cpu_mask_to_apicid_and(), it helps to hide APIC driver
>> details from IOAPIC/HPET/MSI drivers..
>>
>> Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
>> ---
>>  arch/x86/include/asm/hw_irq.h |    1 +
>>  arch/x86/kernel/apic/vector.c |    4 ++++
>>  2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
>> index 7624fffc2822..3d51d74d6c01 100644
>> --- a/arch/x86/include/asm/hw_irq.h
>> +++ b/arch/x86/include/asm/hw_irq.h
>> @@ -116,6 +116,7 @@ struct irq_data;
>>  struct irq_cfg {
>>  	cpumask_var_t		domain;
>>  	cpumask_var_t		old_domain;
>> +	unsigned int		dest_apicid;
>>  	u8			vector;
>>  	u8			move_in_progress : 1;
>>  #ifdef CONFIG_IRQ_REMAP
>> diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
>> index 7562cb15b3bd..287ae4e8d500 100644
>> --- a/arch/x86/kernel/apic/vector.c
>> +++ b/arch/x86/kernel/apic/vector.c
>> @@ -188,6 +188,10 @@ next:
>>  	}
>>  	free_cpumask_var(tmp_mask);
> 
> Lacks a comment what this call is actually doing.
How about this?
/* cache destination APIC IDs into cfg->dest_apicid */
Regards!
Gerry
>   
>> +	if (!err)
>> +		err = apic->cpu_mask_to_apicid_and(mask, cfg->domain,
>> +						   &cfg->dest_apicid);
>> +
> 
> Thanks,
> 
> 	tglx
> 

WARNING: multiple messages have this Message-ID (diff)
From: jiang.liu@linux.intel.com (Jiang Liu)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC Part2 v1 03/21] x86, irq: Save destination CPU ID in irq_cfg
Date: Wed, 17 Sep 2014 10:24:59 +0800	[thread overview]
Message-ID: <5418F0FB.6090004@linux.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1409161046460.4247@nanos>



On 2014/9/17 1:47, Thomas Gleixner wrote:
> 
> 
> On Thu, 11 Sep 2014, Jiang Liu wrote:
> 
>> Cache destination CPU APIC ID into struct irq_cfg when assigning vector
>> for interrupt. Upper layer just needs to read the cached APIC ID instead
>> of calling apic->cpu_mask_to_apicid_and(), it helps to hide APIC driver
>> details from IOAPIC/HPET/MSI drivers..
>>
>> Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com>
>> ---
>>  arch/x86/include/asm/hw_irq.h |    1 +
>>  arch/x86/kernel/apic/vector.c |    4 ++++
>>  2 files changed, 5 insertions(+)
>>
>> diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
>> index 7624fffc2822..3d51d74d6c01 100644
>> --- a/arch/x86/include/asm/hw_irq.h
>> +++ b/arch/x86/include/asm/hw_irq.h
>> @@ -116,6 +116,7 @@ struct irq_data;
>>  struct irq_cfg {
>>  	cpumask_var_t		domain;
>>  	cpumask_var_t		old_domain;
>> +	unsigned int		dest_apicid;
>>  	u8			vector;
>>  	u8			move_in_progress : 1;
>>  #ifdef CONFIG_IRQ_REMAP
>> diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c
>> index 7562cb15b3bd..287ae4e8d500 100644
>> --- a/arch/x86/kernel/apic/vector.c
>> +++ b/arch/x86/kernel/apic/vector.c
>> @@ -188,6 +188,10 @@ next:
>>  	}
>>  	free_cpumask_var(tmp_mask);
> 
> Lacks a comment what this call is actually doing.
How about this?
/* cache destination APIC IDs into cfg->dest_apicid */
Regards!
Gerry
>   
>> +	if (!err)
>> +		err = apic->cpu_mask_to_apicid_and(mask, cfg->domain,
>> +						   &cfg->dest_apicid);
>> +
> 
> Thanks,
> 
> 	tglx
> 

  reply	other threads:[~2014-09-17  2:24 UTC|newest]

Thread overview: 108+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-11 14:03 [RFC Part2 v1 00/21] Enable hierarchy irqdomian on x86 platforms Jiang Liu
2014-09-11 14:03 ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 01/21] irqdomain: Introduce new interfaces to support hierarchy irqdomains Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-16 17:43   ` Thomas Gleixner
2014-09-16 17:43     ` Thomas Gleixner
2014-09-18  7:28     ` Jiang Liu
2014-09-18  7:28       ` Jiang Liu
2014-09-22  8:17     ` [Patch] " Jiang Liu
2014-09-22  8:17       ` Jiang Liu
2014-09-22 17:30       ` Randy Dunlap
2014-09-22 17:30         ` Randy Dunlap
2014-09-24  5:26         ` Jiang Liu
2014-09-24  5:26           ` Jiang Liu
2014-09-24  5:26           ` Jiang Liu
2014-09-23  9:43       ` Joe.C
2014-09-23  9:43         ` Joe.C
2014-09-24  5:55         ` Jiang Liu
2014-09-24  5:55           ` Jiang Liu
2014-09-18  8:48   ` [RFC Part2 v1 01/21] " Joe.C
2014-09-18  8:48     ` Joe.C
2014-09-18  8:58     ` Jiang Liu
2014-09-18  8:58       ` Jiang Liu
2014-09-24  6:55   ` Yasuaki Ishimatsu
2014-09-24  6:55     ` Yasuaki Ishimatsu
2014-09-24  6:55     ` Yasuaki Ishimatsu
2014-09-24  7:23     ` Jiang Liu
2014-09-24  7:23       ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 02/21] genirq: Introduce helper functions to support stacked irq_chip Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-16 17:45   ` Thomas Gleixner
2014-09-16 17:45     ` Thomas Gleixner
2014-09-17  3:07     ` Jiang Liu
2014-09-17  3:07       ` Jiang Liu
2014-09-17 20:58       ` Thomas Gleixner
2014-09-17 20:58         ` Thomas Gleixner
2014-09-18  6:14         ` Jiang Liu
2014-09-18  6:14           ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 03/21] x86, irq: Save destination CPU ID in irq_cfg Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-16 17:47   ` Thomas Gleixner
2014-09-16 17:47     ` Thomas Gleixner
2014-09-17  2:24     ` Jiang Liu [this message]
2014-09-17  2:24       ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 04/21] x86, irq: Use hierarchy irqdomain to manage CPU interrupt vectors Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 05/21] x86, hpet: Use new irqdomain interfaces to allocate/free IRQ Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 06/21] x86, MSI: " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 07/21] x86, uv: " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 08/21] x86, htirq: " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 09/21] x86, dmar: " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 10/21] x86: irq_remapping: Introduce new interfaces to support hierarchy irqdomain Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 11/21] iommu/vt-d: Change prototypes to prepare for enabling " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 12/21] iommu/vt-d: Enhance Intel IR driver to suppport " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 13/21] iommu/amd: Enhance AMD " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 14/21] x86, hpet: Enhance HPET IRQ to support " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-16 18:31   ` Thomas Gleixner
2014-09-16 18:31     ` Thomas Gleixner
2014-09-17  5:16     ` Jiang Liu
2014-09-17  5:16       ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 15/21] x86, MSI: Use hierarchy irqdomain to manage MSI interrupts Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:17   ` Ni, Xun
2014-09-11 14:17     ` Ni, Xun
2014-09-11 14:29     ` Jiang Liu
2014-09-11 14:29       ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 16/21] x86, irq: Directly call native_compose_msi_msg() for DMAR IRQ Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 17/21] x86, htirq: Use hierarchy irqdomain to manage Hypertransport interrupts Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 18/21] iommu/vt-d: Clean up unused MSI related code Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 19/21] iommu/amd: " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 20/21] x86: irq_remapping: " Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-11 14:03 ` [RFC Part2 v1 21/21] x86, irq: Clean up unused MSI related code and interfaces Jiang Liu
2014-09-11 14:03   ` Jiang Liu
2014-09-24  7:59 ` [RFC Part2 v1 00/21] Enable hierarchy irqdomian on x86 platforms Yasuaki Ishimatsu
2014-09-24  7:59   ` Yasuaki Ishimatsu
2014-09-24  7:59   ` Yasuaki Ishimatsu
2014-09-24  8:10   ` Jiang Liu
2014-09-24  8:10     ` Jiang Liu
2014-09-24  8:12     ` Yasuaki Ishimatsu
2014-09-24  8:12       ` Yasuaki Ishimatsu
2014-09-24  8:12       ` Yasuaki Ishimatsu
2014-09-24 19:25   ` Thomas Gleixner
2014-09-24 19:25     ` Thomas Gleixner
2014-09-25  8:15     ` Yasuaki Ishimatsu
2014-09-25  8:15       ` Yasuaki Ishimatsu
2014-09-25  8:15       ` Yasuaki Ishimatsu

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