diff for duplicates of <542972DD.8020700@suse.de> diff --git a/a/1.txt b/N1/1.txt index dd94aab..ce17d5f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,12 +1,12 @@ Hi, -Am 29.09.2014 um 13:48 schrieb zhang.lyra at gmail.com: -> From: "zhizhou.zhang" <zhizhou.zhang@spreadtrum.com> +Am 29.09.2014 um 13:48 schrieb zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: +> From: "zhizhou.zhang" <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> > > Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture. > -> Signed-off-by: zhizhou.zhang <zhizhou.zhang@spreadtrum.com> -> Signed-off-by: chunyan.zhang <chunyan.zhang@spreadtrum.com> +> Signed-off-by: zhizhou.zhang <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> +> Signed-off-by: chunyan.zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org> > --- > arch/arm64/boot/dts/sprd_shark64.dts | 110 ++++++++++++++++++++++++++++++++++ > 1 file changed, 110 insertions(+) @@ -63,28 +63,28 @@ Andreas > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 2 { +> + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 3 { +> + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x3>; @@ -93,7 +93,7 @@ Andreas > + }; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + reg = <0 0x80000000 0 0x20000000>; > + }; @@ -103,7 +103,7 @@ Andreas > + serial1 = &uart1; > + }; > + -> + gic: interrupt-controller at 12001000 { +> + gic: interrupt-controller@12001000 { > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -112,7 +112,7 @@ Andreas > + <0 0x12002000 0 0x1000>; > + }; > + -> + intc:interrupt-controller at 71400000 { +> + intc:interrupt-controller@71400000 { > + compatible = "sprd,intc"; > + #interrupt-cells = <0>; > + interrupt-controller; @@ -131,13 +131,13 @@ Andreas > + clock-frequency = <26000000>; > + }; > + -> + uart0: uart at 70000000 { +> + uart0: uart@70000000 { > + compatible = "sprd,serial"; > + reg = <0 0x70000000 0 0x100>; > + interrupts = <0 2 0xf04>; > + }; > + -> + uart1: uart at 70100000 { +> + uart1: uart@70100000 { > + compatible = "sprd,serial"; > + reg = <0 0x70100000 0 0x100>; > + interrupts = <0 3 0xf04>; @@ -145,5 +145,9 @@ Andreas > +}; -- -SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany -GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg +SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany +GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 689c469..2495bd1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,40 @@ "ref\01411991314-6636-1-git-send-email-zhang.lyra@gmail.com\0" "ref\01411991314-6636-3-git-send-email-zhang.lyra@gmail.com\0" - "From\0afaerber@suse.de (Andreas F\303\244rber)\0" - "Subject\0[PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" + "ref\01411991314-6636-3-git-send-email-zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Andreas F\303\244rber <afaerber-l3A5Bk7waGM@public.gmane.org>\0" + "Subject\0Re: [PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" "Date\0Mon, 29 Sep 2014 16:55:25 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "Cc\0catalin.marinas-5wv7dgnIgG8@public.gmane.org" + gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org + jslaby-AlSwsSmVLrQ@public.gmane.org + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + broonie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + m-karicheri2-l0cyMroinI0@public.gmane.org + pawel.moll-5wv7dgnIgG8@public.gmane.org + artagnon-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + rrichter-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + orsonzhai-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org + geng.ren-lxIno14LUO0EEoCn2XhGlw@public.gmane.org + zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "Hi,\n" "\n" - "Am 29.09.2014 um 13:48 schrieb zhang.lyra at gmail.com:\n" - "> From: \"zhizhou.zhang\" <zhizhou.zhang@spreadtrum.com>\n" + "Am 29.09.2014 um 13:48 schrieb zhang.lyra-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org:\n" + "> From: \"zhizhou.zhang\" <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n" "> \n" "> Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture.\n" "> \n" - "> Signed-off-by: zhizhou.zhang <zhizhou.zhang@spreadtrum.com>\n" - "> Signed-off-by: chunyan.zhang <chunyan.zhang@spreadtrum.com>\n" + "> Signed-off-by: zhizhou.zhang <zhizhou.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n" + "> Signed-off-by: chunyan.zhang <chunyan.zhang-lxIno14LUO0EEoCn2XhGlw@public.gmane.org>\n" "> ---\n" "> arch/arm64/boot/dts/sprd_shark64.dts | 110 ++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 110 insertions(+)\n" @@ -71,28 +91,28 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -101,7 +121,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0 0x80000000 0 0x20000000>;\n" "> +\t};\n" @@ -111,7 +131,7 @@ "> +\t\tserial1 = &uart1;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 12001000 {\n" + "> +\tgic: interrupt-controller@12001000 {\n" "> +\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -120,7 +140,7 @@ "> +\t\t <0 0x12002000 0 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\tintc:interrupt-controller at 71400000 {\n" + "> +\tintc:interrupt-controller@71400000 {\n" "> +\t\tcompatible = \"sprd,intc\";\n" "> +\t\t#interrupt-cells = <0>;\n" "> +\t\tinterrupt-controller;\n" @@ -139,13 +159,13 @@ "> +\t\tclock-frequency = <26000000>;\n" "> +\t};\n" "> +\n" - "> +\tuart0: uart at 70000000 {\n" + "> +\tuart0: uart@70000000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70000000 0 0x100>;\n" "> +\t\tinterrupts = <0 2 0xf04>;\n" "> +\t};\n" "> +\n" - "> +\tuart1: uart at 70100000 {\n" + "> +\tuart1: uart@70100000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70100000 0 0x100>;\n" "> +\t\tinterrupts = <0 3 0xf04>;\n" @@ -153,7 +173,11 @@ "> +};\n" "\n" "-- \n" - "SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany\n" - GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg + "SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N\303\274rnberg, Germany\n" + "GF: Jeff Hawn, Jennifer Guild, Felix Imend\303\266rffer; HRB 16746 AG N\303\274rnberg\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -4a0eba3d6d42b1c0ddf986660b719847f1b61afa9febaa152bd516f360785303 +0cf306b959dfc749643e5a1a8139534a521e430f479897ea5aefbff77d5bcacb
diff --git a/a/1.txt b/N2/1.txt index dd94aab..c13e96c 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,6 +1,6 @@ Hi, -Am 29.09.2014 um 13:48 schrieb zhang.lyra at gmail.com: +Am 29.09.2014 um 13:48 schrieb zhang.lyra@gmail.com: > From: "zhizhou.zhang" <zhizhou.zhang@spreadtrum.com> > > Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture. @@ -63,28 +63,28 @@ Andreas > + #address-cells = <2>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x0>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x1>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 2 { +> + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x2>; > + enable-method = "spin-table"; > + cpu-release-addr = <0x0 0x8000fff8>; > + }; -> + cpu at 3 { +> + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,armv8"; > + reg = <0x0 0x3>; @@ -93,7 +93,7 @@ Andreas > + }; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + reg = <0 0x80000000 0 0x20000000>; > + }; @@ -103,7 +103,7 @@ Andreas > + serial1 = &uart1; > + }; > + -> + gic: interrupt-controller at 12001000 { +> + gic: interrupt-controller@12001000 { > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > + #interrupt-cells = <3>; > + #address-cells = <0>; @@ -112,7 +112,7 @@ Andreas > + <0 0x12002000 0 0x1000>; > + }; > + -> + intc:interrupt-controller at 71400000 { +> + intc:interrupt-controller@71400000 { > + compatible = "sprd,intc"; > + #interrupt-cells = <0>; > + interrupt-controller; @@ -131,13 +131,13 @@ Andreas > + clock-frequency = <26000000>; > + }; > + -> + uart0: uart at 70000000 { +> + uart0: uart@70000000 { > + compatible = "sprd,serial"; > + reg = <0 0x70000000 0 0x100>; > + interrupts = <0 2 0xf04>; > + }; > + -> + uart1: uart at 70100000 { +> + uart1: uart@70100000 { > + compatible = "sprd,serial"; > + reg = <0 0x70100000 0 0x100>; > + interrupts = <0 3 0xf04>; @@ -145,5 +145,5 @@ Andreas > +}; -- -SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany -GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg +SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany +GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg diff --git a/a/content_digest b/N2/content_digest index 689c469..fc2cbb4 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,14 +1,33 @@ "ref\01411991314-6636-1-git-send-email-zhang.lyra@gmail.com\0" "ref\01411991314-6636-3-git-send-email-zhang.lyra@gmail.com\0" - "From\0afaerber@suse.de (Andreas F\303\244rber)\0" - "Subject\0[PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" + "From\0Andreas F\303\244rber <afaerber@suse.de>\0" + "Subject\0Re: [PATCH 2/6] arm64: Add DTS support for Spreadtrum's Shark64 SoC\0" "Date\0Mon, 29 Sep 2014 16:55:25 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0zhang.lyra@gmail.com\0" + "Cc\0catalin.marinas@arm.com" + gregkh@linuxfoundation.org + ijc+devicetree@hellion.org.uk + jslaby@suse.cz + galak@codeaurora.org + broonie@linaro.org + mark.rutland@arm.com + m-karicheri2@ti.com + pawel.moll@arm.com + artagnon@gmail.com + rrichter@cavium.com + robh+dt@kernel.org + will.deacon@arm.com + orsonzhai@gmail.com + geng.ren@spreadtrum.com + zhizhou.zhang@spreadtrum.com + devicetree@vger.kernel.org + linux-kernel@vger.kernel.org + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi,\n" "\n" - "Am 29.09.2014 um 13:48 schrieb zhang.lyra at gmail.com:\n" + "Am 29.09.2014 um 13:48 schrieb zhang.lyra@gmail.com:\n" "> From: \"zhizhou.zhang\" <zhizhou.zhang@spreadtrum.com>\n" "> \n" "> Adds the device tree support for Spreadtrum Shark64 SoC based on ARMv8 architecture.\n" @@ -71,28 +90,28 @@ "> +\t\t#address-cells = <2>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x0>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x1>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x2>;\n" "> +\t\t\tenable-method = \"spin-table\";\n" "> +\t\t\tcpu-release-addr = <0x0 0x8000fff8>;\n" "> +\t\t};\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -101,7 +120,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t\treg = <0 0x80000000 0 0x20000000>;\n" "> +\t};\n" @@ -111,7 +130,7 @@ "> +\t\tserial1 = &uart1;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 12001000 {\n" + "> +\tgic: interrupt-controller@12001000 {\n" "> +\t\tcompatible = \"arm,cortex-a15-gic\", \"arm,cortex-a9-gic\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <0>;\n" @@ -120,7 +139,7 @@ "> +\t\t <0 0x12002000 0 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\tintc:interrupt-controller at 71400000 {\n" + "> +\tintc:interrupt-controller@71400000 {\n" "> +\t\tcompatible = \"sprd,intc\";\n" "> +\t\t#interrupt-cells = <0>;\n" "> +\t\tinterrupt-controller;\n" @@ -139,13 +158,13 @@ "> +\t\tclock-frequency = <26000000>;\n" "> +\t};\n" "> +\n" - "> +\tuart0: uart at 70000000 {\n" + "> +\tuart0: uart@70000000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70000000 0 0x100>;\n" "> +\t\tinterrupts = <0 2 0xf04>;\n" "> +\t};\n" "> +\n" - "> +\tuart1: uart at 70100000 {\n" + "> +\tuart1: uart@70100000 {\n" "> +\t\tcompatible = \"sprd,serial\";\n" "> +\t\treg = <0 0x70100000 0 0x100>;\n" "> +\t\tinterrupts = <0 3 0xf04>;\n" @@ -153,7 +172,7 @@ "> +};\n" "\n" "-- \n" - "SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany\n" - GF: Jeff Hawn, Jennifer Guild, Felix Imend?rffer; HRB 16746 AG N?rnberg + "SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N\303\274rnberg, Germany\n" + "GF: Jeff Hawn, Jennifer Guild, Felix Imend\303\266rffer; HRB 16746 AG N\303\274rnberg" -4a0eba3d6d42b1c0ddf986660b719847f1b61afa9febaa152bd516f360785303 +edb133f9279fdc41703ef0ce4c7f44087202e797b6102604acdfc222d8c42217
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.