From: Leon Alrae <leon.alrae@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: cristian.cuna@imgtec.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 06/20] target-mips: add MSA opcode enum
Date: Fri, 10 Oct 2014 10:26:39 +0100 [thread overview]
Message-ID: <5437A64F.5000605@imgtec.com> (raw)
In-Reply-To: <1405331763-57126-7-git-send-email-yongbok.kim@imgtec.com>
On 14/07/2014 10:55, Yongbok Kim wrote:
> add MSA opcode enum
>
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
> target-mips/translate.c | 248 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 248 insertions(+), 0 deletions(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index cccbc44..6b4a82c 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -108,6 +108,8 @@ enum {
> OPC_SDC2 = (0x3E << 26),
> /* MDMX ASE specific */
> OPC_MDMX = (0x1E << 26),
> + /* MSA ASE, same as MDMX */
> + OPC_MSA = OPC_MDMX,
> /* Cache and prefetch */
> OPC_CACHE = (0x2F << 26),
> OPC_PREF = (0x33 << 26),
> @@ -128,10 +130,12 @@ enum {
> OPC_ROTR = OPC_SRL | (1 << 21),
> OPC_SRA = 0x03 | OPC_SPECIAL,
> OPC_SLLV = 0x04 | OPC_SPECIAL,
> + OPC_MSA_S05 = 0x05 | OPC_SPECIAL,
> OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */
> OPC_ROTRV = OPC_SRLV | (1 << 6),
> OPC_SRAV = 0x07 | OPC_SPECIAL,
> OPC_DSLLV = 0x14 | OPC_SPECIAL,
> + OPC_MSA_S15 = 0x15 | OPC_SPECIAL,
OPC_MSA_S05 and OPC_MSA_S15 seem to be unused.
> OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */
> OPC_DROTRV = OPC_DSRLV | (1 << 6),
> OPC_DSRAV = 0x17 | OPC_SPECIAL,
> @@ -835,6 +839,8 @@ enum {
> OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
> OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
> OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
> + OPC_MSA_BZ_V = (0x0B << 21) | OPC_CP1,
> + OPC_MSA_BNZ_V = (0x0F << 21) | OPC_CP1,
> OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
> OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
> OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
> @@ -842,6 +848,14 @@ enum {
> OPC_W_FMT = (FMT_W << 21) | OPC_CP1,
> OPC_L_FMT = (FMT_L << 21) | OPC_CP1,
> OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
> + OPC_MSA_BZ_B = (0x18 << 21) | OPC_CP1,
> + OPC_MSA_BZ_H = (0x19 << 21) | OPC_CP1,
> + OPC_MSA_BZ_W = (0x1A << 21) | OPC_CP1,
> + OPC_MSA_BZ_D = (0x1B << 21) | OPC_CP1,
> + OPC_MSA_BNZ_B = (0x1C << 21) | OPC_CP1,
> + OPC_MSA_BNZ_H = (0x1D << 21) | OPC_CP1,
> + OPC_MSA_BNZ_W = (0x1E << 21) | OPC_CP1,
> + OPC_MSA_BNZ_D = (0x1F << 21) | OPC_CP1,
Extra whitespace ^
> };
>
> #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
> @@ -1000,6 +1014,240 @@ enum {
> OPC_NMSUB_PS= 0x3E | OPC_CP3,
> };
>
> +/* MSA Opcodes */
> +
> +#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
> +enum {
> + OPC_MSA_I8_00 = 0x00 | OPC_MSA,
> + OPC_MSA_I8_01 = 0x01 | OPC_MSA,
> + OPC_MSA_I8_02 = 0x02 | OPC_MSA,
> + OPC_MSA_I5_06 = 0x06 | OPC_MSA,
> + OPC_MSA_I5_07 = 0x07 | OPC_MSA,
> + OPC_MSA_BIT_09 = 0x09 | OPC_MSA,
> + OPC_MSA_BIT_0A = 0x0A | OPC_MSA,
> + OPC_MSA_3R_0D = 0x0D | OPC_MSA,
> + OPC_MSA_3R_0E = 0x0E | OPC_MSA,
> + OPC_MSA_3R_0F = 0x0F | OPC_MSA,
> + OPC_MSA_3R_10 = 0x10 | OPC_MSA,
> + OPC_MSA_3R_11 = 0x11 | OPC_MSA,
> + OPC_MSA_3R_12 = 0x12 | OPC_MSA,
> + OPC_MSA_3R_13 = 0x13 | OPC_MSA,
> + OPC_MSA_3R_14 = 0x14 | OPC_MSA,
> + OPC_MSA_3R_15 = 0x15 | OPC_MSA,
> + OPC_MSA_ELM = 0x19 | OPC_MSA,
> + OPC_MSA_3RF_1A = 0x1A | OPC_MSA,
> + OPC_MSA_3RF_1B = 0x1B | OPC_MSA,
> + OPC_MSA_3RF_1C = 0x1C | OPC_MSA,
> + OPC_MSA_VEC = 0x1E | OPC_MSA,
> +
> + /* MI10 instruction */
> + OPC_MSA_LD_B = (0x20) | OPC_MSA,
> + OPC_MSA_LD_H = (0x21) | OPC_MSA,
> + OPC_MSA_LD_W = (0x22) | OPC_MSA,
> + OPC_MSA_LD_D = (0x23) | OPC_MSA,
> + OPC_MSA_ST_B = (0x24) | OPC_MSA,
> + OPC_MSA_ST_H = (0x25) | OPC_MSA,
> + OPC_MSA_ST_W = (0x26) | OPC_MSA,
> + OPC_MSA_ST_D = (0x27) | OPC_MSA,
> +};
> +
> +enum {
> + /* I5 instruction df(bits 22..21) = _b, _h, _w, _d */
> + OPC_MSA_ADDVI_df = (0x0 << 23) | OPC_MSA_I5_06,
> + OPC_MSA_CEQI_df = (0x0 << 23) | OPC_MSA_I5_07,
> + OPC_MSA_SUBVI_df = (0x1 << 23) | OPC_MSA_I5_06,
> + OPC_MSA_MAXI_S_df = (0x2 << 23) | OPC_MSA_I5_06,
> + OPC_MSA_CLTI_S_df = (0x2 << 23) | OPC_MSA_I5_07,
> + OPC_MSA_MAXI_U_df = (0x3 << 23) | OPC_MSA_I5_06,
> + OPC_MSA_CLTI_U_df = (0x3 << 23) | OPC_MSA_I5_07,
> + OPC_MSA_MINI_S_df = (0x4 << 23) | OPC_MSA_I5_06,
> + OPC_MSA_CLEI_S_df = (0x4 << 23) | OPC_MSA_I5_07,
> + OPC_MSA_MINI_U_df = (0x5 << 23) | OPC_MSA_I5_06,
> + OPC_MSA_CLEI_U_df = (0x5 << 23) | OPC_MSA_I5_07,
> + OPC_MSA_LDI_df = (0x6 << 23) | OPC_MSA_I5_07,
> +
> + /* I8 instruction */
> + OPC_MSA_ANDI_B = (0x0 << 24) | OPC_MSA_I8_00,
> + OPC_MSA_BMNZI_B = (0x0 << 24) | OPC_MSA_I8_01,
> + OPC_MSA_SHF_B = (0x0 << 24) | OPC_MSA_I8_02,
> + OPC_MSA_ORI_B = (0x1 << 24) | OPC_MSA_I8_00,
> + OPC_MSA_BMZI_B = (0x1 << 24) | OPC_MSA_I8_01,
> + OPC_MSA_SHF_H = (0x1 << 24) | OPC_MSA_I8_02,
> + OPC_MSA_NORI_B = (0x2 << 24) | OPC_MSA_I8_00,
> + OPC_MSA_BSELI_B = (0x2 << 24) | OPC_MSA_I8_01,
> + OPC_MSA_SHF_W = (0x2 << 24) | OPC_MSA_I8_02,
> + OPC_MSA_XORI_B = (0x3 << 24) | OPC_MSA_I8_00,
> +
> + /* VEC/2R/2RF instruction */
> + OPC_MSA_AND_V = (0x00 << 21) | OPC_MSA_VEC,
> + OPC_MSA_OR_V = (0x01 << 21) | OPC_MSA_VEC,
> + OPC_MSA_NOR_V = (0x02 << 21) | OPC_MSA_VEC,
> + OPC_MSA_XOR_V = (0x03 << 21) | OPC_MSA_VEC,
> + OPC_MSA_BMNZ_V = (0x04 << 21) | OPC_MSA_VEC,
> + OPC_MSA_BMZ_V = (0x05 << 21) | OPC_MSA_VEC,
> + OPC_MSA_BSEL_V = (0x06 << 21) | OPC_MSA_VEC,
> +
> + OPC_MSA_2R = (0x18 << 21) | OPC_MSA_VEC,
> + OPC_MSA_2RF = (0x19 << 21) | OPC_MSA_VEC,
> +
> + /* 2R instruction df(bits 17..16) = _b, _h, _w, _d */
> + OPC_MSA_FILL_df = (0x00 << 16) | OPC_MSA_2R,
> + OPC_MSA_PCNT_df = (0x04 << 16) | OPC_MSA_2R,
> + OPC_MSA_NLOC_df = (0x08 << 16) | OPC_MSA_2R,
> + OPC_MSA_NLZC_df = (0x0C << 16) | OPC_MSA_2R,
> +
> + /* 2RF instruction df(bit 16) = _w, _d */
> + OPC_MSA_FCLASS_df = (0x00 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FTRUNC_S_df = (0x02 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FTRUNC_U_df = (0x04 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FSQRT_df = (0x06 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FRSQRT_df = (0x08 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FRCP_df = (0x0A << 16) | OPC_MSA_2RF,
> + OPC_MSA_FRINT_df = (0x0C << 16) | OPC_MSA_2RF,
> + OPC_MSA_FRLOG2_df = (0x0E << 16) | OPC_MSA_2RF,
> + OPC_MSA_FEXUPL_df = (0x10 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FEXUPR_df = (0x12 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FFQL_df = (0x14 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FFQR_df = (0x16 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FINT_S_df = (0x18 << 16) | OPC_MSA_2RF,
> + OPC_MSA_FINT_U_df = (0x1A << 16) | OPC_MSA_2RF,
> + OPC_MSA_FFINT_S_df = (0x1C << 16) | OPC_MSA_2RF,
> + OPC_MSA_FFINT_U_df = (0x1E << 16) | OPC_MSA_2RF,
> +
> + /* 3R instruction df(bits 22..21) = _b, _h, _w, d */
> + OPC_MSA_SLL_df = (0x0 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_ADDV_df = (0x0 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_CEQ_df = (0x0 << 23) | OPC_MSA_3R_0F,
> + OPC_MSA_ADD_A_df = (0x0 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_SUBS_S_df = (0x0 << 23) | OPC_MSA_3R_11,
> + OPC_MSA_MULV_df = (0x0 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_DOTP_S_df = (0x0 << 23) | OPC_MSA_3R_13,
> + OPC_MSA_SLD_df = (0x0 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_VSHF_df = (0x0 << 23) | OPC_MSA_3R_15,
> + OPC_MSA_SRA_df = (0x1 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_SUBV_df = (0x1 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_ADDS_A_df = (0x1 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_SUBS_U_df = (0x1 << 23) | OPC_MSA_3R_11,
> + OPC_MSA_MADDV_df = (0x1 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_DOTP_U_df = (0x1 << 23) | OPC_MSA_3R_13,
> + OPC_MSA_SPLAT_df = (0x1 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_SRAR_df = (0x1 << 23) | OPC_MSA_3R_15,
> + OPC_MSA_SRL_df = (0x2 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_MAX_S_df = (0x2 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_CLT_S_df = (0x2 << 23) | OPC_MSA_3R_0F,
> + OPC_MSA_ADDS_S_df = (0x2 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
> + OPC_MSA_MSUBV_df = (0x2 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_DPADD_S_df = (0x2 << 23) | OPC_MSA_3R_13,
> + OPC_MSA_PCKEV_df = (0x2 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_SRLR_df = (0x2 << 23) | OPC_MSA_3R_15,
> + OPC_MSA_BCLR_df = (0x3 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_MAX_U_df = (0x3 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_CLT_U_df = (0x3 << 23) | OPC_MSA_3R_0F,
> + OPC_MSA_ADDS_U_df = (0x3 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
> + OPC_MSA_DPADD_U_df = (0x3 << 23) | OPC_MSA_3R_13,
> + OPC_MSA_PCKOD_df = (0x3 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_BSET_df = (0x4 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_MIN_S_df = (0x4 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_CLE_S_df = (0x4 << 23) | OPC_MSA_3R_0F,
> + OPC_MSA_AVE_S_df = (0x4 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_ASUB_S_df = (0x4 << 23) | OPC_MSA_3R_11,
> + OPC_MSA_DIV_S_df = (0x4 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_DPSUB_S_df = (0x4 << 23) | OPC_MSA_3R_13,
> + OPC_MSA_ILVL_df = (0x4 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_HADD_S_df = (0x4 << 23) | OPC_MSA_3R_15,
> + OPC_MSA_BNEG_df = (0x5 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_MIN_U_df = (0x5 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_CLE_U_df = (0x5 << 23) | OPC_MSA_3R_0F,
> + OPC_MSA_AVE_U_df = (0x5 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
> + OPC_MSA_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_DPSUB_U_df = (0x5 << 23) | OPC_MSA_3R_13,
> + OPC_MSA_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_HADD_U_df = (0x5 << 23) | OPC_MSA_3R_15,
> + OPC_MSA_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_HSUB_S_df = (0x6 << 23) | OPC_MSA_3R_15,
> + OPC_MSA_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
> + OPC_MSA_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
> + OPC_MSA_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
> + OPC_MSA_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
> + OPC_MSA_ILVOD_df = (0x7 << 23) | OPC_MSA_3R_14,
> + OPC_MSA_HSUB_U_df = (0x7 << 23) | OPC_MSA_3R_15,
> +
> + /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
> + OPC_MSA_SLDI_df = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> + OPC_MSA_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
> + OPC_MSA_SPLATI_df = (0x1 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> + OPC_MSA_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
> + OPC_MSA_COPY_S_df = (0x2 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> + OPC_MSA_MOVE_V = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
> + OPC_MSA_COPY_U_df = (0x3 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> + OPC_MSA_INSERT_df = (0x4 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> + OPC_MSA_INSVE_df = (0x5 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> +
> + /* 3RF instruction _df(bit 21) = _w, _d */
> + OPC_MSA_FCAF_df = (0x0 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FADD_df = (0x0 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FCUN_df = (0x1 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FSUB_df = (0x1 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FCOR_df = (0x1 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FCEQ_df = (0x2 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMUL_df = (0x2 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FCUNE_df = (0x2 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FCUEQ_df = (0x3 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FDIV_df = (0x3 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FCNE_df = (0x3 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FCLT_df = (0x4 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMADD_df = (0x4 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_MUL_Q_df = (0x4 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FCULT_df = (0x5 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMSUB_df = (0x5 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_MADD_Q_df = (0x5 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FCLE_df = (0x6 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_MSUB_Q_df = (0x6 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FCULE_df = (0x7 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FEXP2_df = (0x7 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FSAF_df = (0x8 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FEXDO_df = (0x8 << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FSUN_df = (0x9 << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FSOR_df = (0x9 << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FSEQ_df = (0xA << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FTQ_df = (0xA << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_FSUNE_df = (0xA << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FSUEQ_df = (0xB << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FSNE_df = (0xB << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FSLT_df = (0xC << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMIN_df = (0xC << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_MULR_Q_df = (0xC << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FSULT_df = (0xD << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMIN_A_df = (0xD << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_MADDR_Q_df = (0xD << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FSLE_df = (0xE << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMAX_df = (0xE << 22) | OPC_MSA_3RF_1B,
> + OPC_MSA_MSUBR_Q_df = (0xE << 22) | OPC_MSA_3RF_1C,
> + OPC_MSA_FSULE_df = (0xF << 22) | OPC_MSA_3RF_1A,
> + OPC_MSA_FMAX_A_df = (0xF << 22) | OPC_MSA_3RF_1B,
> +
> + /* BIT instruction df(bits 22..16) = _B _H _W _D */
> + OPC_MSA_SLLI_df = (0x0 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_SAT_S_df = (0x0 << 23) | OPC_MSA_BIT_0A,
> + OPC_MSA_SRAI_df = (0x1 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_SAT_U_df = (0x1 << 23) | OPC_MSA_BIT_0A,
> + OPC_MSA_SRLI_df = (0x2 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_SRARI_df = (0x2 << 23) | OPC_MSA_BIT_0A,
> + OPC_MSA_BCLRI_df = (0x3 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_SRLRI_df = (0x3 << 23) | OPC_MSA_BIT_0A,
> + OPC_MSA_BSETI_df = (0x4 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_BNEGI_df = (0x5 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_BINSLI_df = (0x6 << 23) | OPC_MSA_BIT_09,
> + OPC_MSA_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
> +};
> +
> /* global register indices */
> static TCGv_ptr cpu_env;
> static TCGv cpu_gpr[32], cpu_PC;
>
Otherwise it looks good to me:
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Leon
next prev parent reply other threads:[~2014-10-10 9:26 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-14 9:55 [Qemu-devel] [PATCH 00/20] target-mips: add MSA module Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 01/20] target-mips: add MSA defines and data structure Yongbok Kim
2014-10-22 11:35 ` James Hogan
2014-10-24 9:35 ` Yongbok Kim
2014-10-24 12:57 ` Leon Alrae
2014-10-22 13:15 ` James Hogan
2014-07-14 9:55 ` [Qemu-devel] [PATCH 02/20] target-mips: add MSA exceptions Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 03/20] target-mips: move common funcs to cpu.h Yongbok Kim
2014-10-10 9:22 ` Leon Alrae
2014-07-14 9:55 ` [Qemu-devel] [PATCH 04/20] target-mips: add 8, 16, 32, 64 bits load and store Yongbok Kim
2014-10-10 9:26 ` Leon Alrae
2014-07-14 9:55 ` [Qemu-devel] [PATCH 05/20] target-mips: stop translation after ctc1 Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 06/20] target-mips: add MSA opcode enum Yongbok Kim
2014-10-10 9:26 ` Leon Alrae [this message]
2014-10-22 12:18 ` James Hogan
2014-07-14 9:55 ` [Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa register Yongbok Kim
2014-10-22 13:21 ` James Hogan
2014-07-14 9:55 ` [Qemu-devel] [PATCH 08/20] target-mips: add msa_helper.c Yongbok Kim
2014-10-10 9:27 ` Leon Alrae
2014-10-22 15:29 ` James Hogan
2014-07-14 9:55 ` [Qemu-devel] [PATCH 09/20] target-mips: add MSA branch instructions Yongbok Kim
2014-10-10 14:13 ` Leon Alrae
2014-10-28 23:05 ` James Hogan
2014-07-14 9:55 ` [Qemu-devel] [PATCH 10/20] target-mips: add MSA I8 format instructions Yongbok Kim
2014-10-28 23:54 ` James Hogan
2014-07-14 9:55 ` [Qemu-devel] [PATCH 11/20] target-mips: add MSA I5 " Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 12/20] target-mips: add MSA BIT " Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 13/20] target-mips: add MSA 3R " Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 14/20] target-mips: add MSA ELM " Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 15/20] target-mips: add MSA 3RF " Yongbok Kim
2014-07-14 9:55 ` [Qemu-devel] [PATCH 16/20] target-mips: add MSA VEC/2R " Yongbok Kim
2014-07-14 9:56 ` [Qemu-devel] [PATCH 17/20] target-mips: add MSA 2RF " Yongbok Kim
2014-07-14 9:56 ` [Qemu-devel] [PATCH 18/20] target-mips: add MSA MI10 " Yongbok Kim
2014-07-14 9:56 ` [Qemu-devel] [PATCH 19/20] disas/mips.c: disassemble MSA instructions Yongbok Kim
2014-07-14 9:56 ` [Qemu-devel] [PATCH 20/20] target-mips: add MSA support to mips32r5-generic Yongbok Kim
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