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From: James Hogan <james.hogan@imgtec.com>
To: Yongbok Kim <yongbok.kim@imgtec.com>, qemu-devel@nongnu.org
Cc: cristian.cuna@imgtec.com, leon.alrae@imgtec.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa register
Date: Wed, 22 Oct 2014 14:21:16 +0100	[thread overview]
Message-ID: <5447AF4C.7070601@imgtec.com> (raw)
In-Reply-To: <1405331763-57126-8-git-send-email-yongbok.kim@imgtec.com>

Hi,

On 14/07/14 10:55, Yongbok Kim wrote:
> +static const char * const msaregnames[] = {
> +    "w0.d0",  "w0.d1",  "w1.d0",  "w1.d1",
> +    "w2.d0",  "w2.d1",  "w3.d0",  "w3.d1",
> +    "w4.d0",  "w4.d1",  "w4.d0",  "w4.d1",

I think those last 2 should be w5.d0 and w5.d1

> +static inline int check_msa_access(CPUMIPSState *env, DisasContext *ctx,
> +                                    int wt, int ws, int wd)
> +{
> +    if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
> +                 !(ctx->hflags & MIPS_HFLAG_F64))) {
> +        generate_exception(ctx, EXCP_RI);
> +        return 0;
> +    }
> +
> +    if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
> +        if (ctx->insn_flags & ASE_MSA) {
> +            generate_exception(ctx, EXCP_MSADIS);
> +            return 0;
> +        } else {
> +            generate_exception(ctx, EXCP_RI);
> +            return 0;
> +        }
> +    }
> +
> +    if (env->active_msa.msair & MSAIR_WRP_BIT) {
> +        int curr_request  = 0;
> +        if (wd != -1) {
> +            curr_request |= (1 << wd);
> +        }
> +        if (wt != -1) {
> +            curr_request |= (1 << wt);
> +        }
> +        if (ws != -1) {
> +            curr_request |= (1 << ws);
> +        }
> +        env->active_msa.msarequest = curr_request
> +                & (~env->active_msa.msaaccess | env->active_msa.msasave);
> +        if (unlikely(env->active_msa.msarequest != 0)) {

Are you sure it's safe to access env here during code generation? How do
you guarantee the values at translation time match the values at run time?

> +            generate_exception(ctx, EXCP_MSADIS);
> +            return 0;
> +        }
> +    }
> +    return 1;
> +}

newline between functions?

> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index 29dc2ef..9e0f67b 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -688,3 +688,48 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
>                               (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
>                               (0x1 << CP0MVPC1_PCP1);
>  }
> +
> +static void msa_reset(CPUMIPSState *env)
> +{
> +#ifdef CONFIG_USER_ONLY
> +    /* MSA access enabled */
> +    env->CP0_Config5 |= 1 << CP0C5_MSAEn;
> +
> +    /* DSP and CP1 enabled, 64-bit FPRs */
> +    env->CP0_Status |= (1 << CP0St_MX);
> +    env->hflags |= MIPS_HFLAG_DSP;

why do you enable DSP?

> +    env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
> +    env->hflags |= MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X;

shouldn't that depend on the program being loaded, and whether it's
built for fp32 or fp64?

> +#endif
> +
> +    /* Vector register partitioning not implemented */
> +    env->active_msa.msair = 0;
> +    env->active_msa.msaaccess  = 0xffffffff;

the reset state is 0 according to the manual. Maybe this should depend
on CONFIG_USER_ONLY.

Cheers
James

  reply	other threads:[~2014-10-22 13:21 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-07-14  9:55 [Qemu-devel] [PATCH 00/20] target-mips: add MSA module Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 01/20] target-mips: add MSA defines and data structure Yongbok Kim
2014-10-22 11:35   ` James Hogan
2014-10-24  9:35     ` Yongbok Kim
2014-10-24 12:57       ` Leon Alrae
2014-10-22 13:15   ` James Hogan
2014-07-14  9:55 ` [Qemu-devel] [PATCH 02/20] target-mips: add MSA exceptions Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 03/20] target-mips: move common funcs to cpu.h Yongbok Kim
2014-10-10  9:22   ` Leon Alrae
2014-07-14  9:55 ` [Qemu-devel] [PATCH 04/20] target-mips: add 8, 16, 32, 64 bits load and store Yongbok Kim
2014-10-10  9:26   ` Leon Alrae
2014-07-14  9:55 ` [Qemu-devel] [PATCH 05/20] target-mips: stop translation after ctc1 Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 06/20] target-mips: add MSA opcode enum Yongbok Kim
2014-10-10  9:26   ` Leon Alrae
2014-10-22 12:18   ` James Hogan
2014-07-14  9:55 ` [Qemu-devel] [PATCH 07/20] target-mips: add msa_reset(), global msa register Yongbok Kim
2014-10-22 13:21   ` James Hogan [this message]
2014-07-14  9:55 ` [Qemu-devel] [PATCH 08/20] target-mips: add msa_helper.c Yongbok Kim
2014-10-10  9:27   ` Leon Alrae
2014-10-22 15:29   ` James Hogan
2014-07-14  9:55 ` [Qemu-devel] [PATCH 09/20] target-mips: add MSA branch instructions Yongbok Kim
2014-10-10 14:13   ` Leon Alrae
2014-10-28 23:05   ` James Hogan
2014-07-14  9:55 ` [Qemu-devel] [PATCH 10/20] target-mips: add MSA I8 format instructions Yongbok Kim
2014-10-28 23:54   ` James Hogan
2014-07-14  9:55 ` [Qemu-devel] [PATCH 11/20] target-mips: add MSA I5 " Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 12/20] target-mips: add MSA BIT " Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 13/20] target-mips: add MSA 3R " Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 14/20] target-mips: add MSA ELM " Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 15/20] target-mips: add MSA 3RF " Yongbok Kim
2014-07-14  9:55 ` [Qemu-devel] [PATCH 16/20] target-mips: add MSA VEC/2R " Yongbok Kim
2014-07-14  9:56 ` [Qemu-devel] [PATCH 17/20] target-mips: add MSA 2RF " Yongbok Kim
2014-07-14  9:56 ` [Qemu-devel] [PATCH 18/20] target-mips: add MSA MI10 " Yongbok Kim
2014-07-14  9:56 ` [Qemu-devel] [PATCH 19/20] disas/mips.c: disassemble MSA instructions Yongbok Kim
2014-07-14  9:56 ` [Qemu-devel] [PATCH 20/20] target-mips: add MSA support to mips32r5-generic Yongbok Kim

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