Re: [PATCH RFC 0/2] Indirect Fast Memory registration support

[Steve Wise <swise-7bPotxP6k4+P2YhJcF5u+vpXobYPEAuW@public.gmane.org>]

On 10/13/2014 6:18 AM, Sagi Grimberg wrote:
> On 10/13/2014 11:48 AM, Bart Van Assche wrote:
>> On 10/12/14 21:43, Or Gerlitz wrote:
>>> Sean, Bart - any comment on the API before Sagi sits down to code the
>>> iSER changes?
>>
>> Hello Or,
>
> Hey Bart,
>
>>
>> Will this API ever be supported by other Mellanox RDMA drivers than
>> mlx5, e.g. mlx4 ?
>
> Well, unfortunately mlx4 micro-architecture does not support
> indirect memory registration. IMHO, simulating it in SW/FW is
> not feasible.
>
>> Will this API ever be supported by a Mellanox HCA that
>> supports RoCE ?
>
> Yes, mlx5 will support RoCE in the future. Moreover AFAIK future
> Mellanox HCAs will keep supporting this technology as it is useful
> for other use-cases as well.
>
>> Additionally, do you perhaps know whether any other RDMA
>> vendors have plans to implement this API for their RDMA HCA's ?
>
> I can't comment on other vendors plans...
> Maybe once this feature is included they will consider it... ;)
>

cxgb4 currently does not support this.  I'm not sure if it could be done 
given the hw architecture.

Steve.
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