From: Qais Yousef <qais.yousef@imgtec.com>
To: Andrew Bresticker <abrestic@chromium.org>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
"Ian Campbell" <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
John Crispin <blogic@openwrt.org>,
David Daney <ddaney.cavm@gmail.com>,
Linux-MIPS <linux-mips@linux-mips.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V3 2/4] of: Add binding document for MIPS GIC
Date: Wed, 29 Oct 2014 17:05:13 +0000 [thread overview]
Message-ID: <54511E49.6090907@imgtec.com> (raw)
In-Reply-To: <CAL1qeaGm1Ma=B-gJV2ovnLNYFooq6bv12rODq4d8cGtKLeNy-g@mail.gmail.com>
On 10/29/2014 04:56 PM, Andrew Bresticker wrote:
> On Wed, Oct 29, 2014 at 4:01 AM, Qais Yousef <qais.yousef@imgtec.com> wrote:
>> On 10/29/2014 12:12 AM, Andrew Bresticker wrote:
>>> +- mti,available-cpu-vectors : Specifies the list of CPU interrupt vectors
>>> + to which the GIC may route interrupts. May contain up to 6 entries,
>>> one
>>> + for each of the CPU's hardware interrupt vectors. Valid values are 2 -
>>> 7.
>>> + This property is ignored if the CPU is started in EIC mode.
>>> +
>>
>> Wouldn't it be better to have this in the reversed sense ie:
>> mti,nonavailable-cpu-vectors? I think the assumption that by default they're
>> all available unless something else is connected to them which is unlikely
>> in most cases. It can be made optional property then.
>>
>> I don't have a strong opinion about it though.
> Actually, I think I like the reversed sense as well. Perhaps
> "mti,reserved-cpu-vectors"?
Yep that's a better wording for sure :)
WARNING: multiple messages have this Message-ID (diff)
From: Qais Yousef <qais.yousef-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
To: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: Ralf Baechle <ralf-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Thomas Gleixner <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Daniel Lezcano
<daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>,
David Daney <ddaney.cavm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Linux-MIPS <linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org>,
"devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Subject: Re: [PATCH V3 2/4] of: Add binding document for MIPS GIC
Date: Wed, 29 Oct 2014 17:05:13 +0000 [thread overview]
Message-ID: <54511E49.6090907@imgtec.com> (raw)
In-Reply-To: <CAL1qeaGm1Ma=B-gJV2ovnLNYFooq6bv12rODq4d8cGtKLeNy-g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 10/29/2014 04:56 PM, Andrew Bresticker wrote:
> On Wed, Oct 29, 2014 at 4:01 AM, Qais Yousef <qais.yousef-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
>> On 10/29/2014 12:12 AM, Andrew Bresticker wrote:
>>> +- mti,available-cpu-vectors : Specifies the list of CPU interrupt vectors
>>> + to which the GIC may route interrupts. May contain up to 6 entries,
>>> one
>>> + for each of the CPU's hardware interrupt vectors. Valid values are 2 -
>>> 7.
>>> + This property is ignored if the CPU is started in EIC mode.
>>> +
>>
>> Wouldn't it be better to have this in the reversed sense ie:
>> mti,nonavailable-cpu-vectors? I think the assumption that by default they're
>> all available unless something else is connected to them which is unlikely
>> in most cases. It can be made optional property then.
>>
>> I don't have a strong opinion about it though.
> Actually, I think I like the reversed sense as well. Perhaps
> "mti,reserved-cpu-vectors"?
Yep that's a better wording for sure :)
--
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next prev parent reply other threads:[~2014-10-29 17:05 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-29 0:12 [PATCH V3 0/4] MIPS: GIC device-tree support Andrew Bresticker
2014-10-29 0:12 ` [PATCH V3 1/4] of: Add vendor prefix for MIPS Technologies, Inc Andrew Bresticker
2014-10-29 0:12 ` [PATCH V3 2/4] of: Add binding document for MIPS GIC Andrew Bresticker
2014-10-29 9:21 ` James Hogan
2014-10-29 9:21 ` James Hogan
2014-10-29 16:55 ` Andrew Bresticker
2014-10-29 17:13 ` James Hogan
2014-10-29 17:25 ` Andrew Bresticker
2014-10-29 21:34 ` James Hogan
2014-10-29 18:01 ` Mark Rutland
2014-10-29 11:01 ` Qais Yousef
2014-10-29 11:01 ` Qais Yousef
2014-10-29 16:56 ` Andrew Bresticker
2014-10-29 16:56 ` Andrew Bresticker
2014-10-29 17:05 ` Qais Yousef [this message]
2014-10-29 17:05 ` Qais Yousef
2014-10-29 11:09 ` Qais Yousef
2014-10-29 11:09 ` Qais Yousef
2014-10-29 17:08 ` Andrew Bresticker
2014-10-29 17:23 ` Qais Yousef
2014-10-29 17:23 ` Qais Yousef
2014-10-29 17:46 ` Mark Rutland
2014-10-29 0:12 ` [PATCH V3 3/4] irqchip: mips-gic: Add device-tree support Andrew Bresticker
2014-10-29 0:12 ` [PATCH V3 4/4] clocksource: " Andrew Bresticker
2014-10-29 0:12 ` Andrew Bresticker
2014-10-29 17:51 ` Mark Rutland
2014-11-04 23:49 ` Andrew Bresticker
2014-11-04 23:49 ` Andrew Bresticker
2014-10-29 8:09 ` [PATCH V3 0/4] MIPS: GIC " Arnd Bergmann
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