* [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx
@ 2014-10-31 2:33 Ganesan, Aravind
0 siblings, 0 replies; 4+ messages in thread
From: Ganesan, Aravind @ 2014-10-31 2:33 UTC (permalink / raw)
To: freedreno, Rob Clark; +Cc: linux-arm-msm, dri-devel, rishib, Jordan Crouse
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.
Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org>
---
Resend in patch-set format and with dri-devel@lists.freedesktop.org on
the CC.
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 103 +++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130
++++++++++++++++++++++++++++++++
3 files changed, 244 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 6c4a91a..9713aef9 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -2,6 +2,8 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
gpu_read(gpu, REG_A3XX_RBBM_STATUS));
adreno_dump(gpu);
}
+/* Register offset defines for A3XX */
+static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
+ REG_A3XX_CP_PFP_UCODE_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
+ REG_A3XX_CP_PFP_UCODE_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
+ REG_A3XX_CP_PROTECT_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
+ REG_A3XX_RBBM_PERFCTR_CTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
+ REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
+ REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
+ REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
+ REG_A3XX_RBBM_INT_0_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
+ REG_A3XX_RBBM_AHB_ERROR_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,
+ REG_A3XX_RBBM_INT_CLEAR_CMD),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,
+ REG_A3XX_VPC_VPC_DEBUG_RAM_SEL),
+ REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ,
+ REG_A3XX_VPC_VPC_DEBUG_RAM_READ),
+ REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
+ REG_A3XX_VSC_PIPE_DATA_ADDRESS_0),
+ REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
+ REG_A3XX_VSC_PIPE_DATA_LENGTH_7),
+ REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS,
+ REG_A3XX_VSC_SIZE_ADDRESS),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_0_0,
+ REG_A3XX_VFD_FETCH_INSTR_0_0),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_1_F,
+ REG_A3XX_VFD_FETCH_INSTR_1_F),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
+ REG_A3XX_SP_VS_PVT_MEM_ADDR_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
+ REG_A3XX_SP_FS_PVT_MEM_ADDR_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG,
+ REG_A3XX_SP_VS_OBJ_START_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG,
+ REG_A3XX_SP_FS_OBJ_START_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2,
+ REG_A3XX_RBBM_PM_OVERRIDE2),
+ REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2),
+ REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT,
+ REG_A3XX_SQ_GPR_MANAGEMENT),
+ REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT,
+ REG_A3XX_SQ_INST_STORE_MANAGMENT),
+ REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD,
+ REG_A3XX_RBBM_SW_RESET_CMD),
+ REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0,
+ REG_A3XX_UCHE_CACHE_INVALIDATE0_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
+ REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
+ REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI),
+};
+
+static const struct adreno_reg_offsets reg_offsets = {
+ .offsets = a3xx_register_offsets,
+};
static const struct adreno_gpu_funcs funcs = {
.base = {
@@ -461,6 +563,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
adreno_gpu->registers = a3xx_registers;
+ adreno_gpu->reg_offsets = ®_offsets;
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
if (ret)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index a74794b..82619b1 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -2,6 +2,8 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -55,19 +57,21 @@ int adreno_hw_init(struct msm_gpu *gpu)
DBG("%s", gpu->name);
/* Setup REG_CP_RB_CNTL: */
- gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
/* size is log2(quad-words): */
AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
/* Setup ringbuffer address: */
- gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
- gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
+ rbmemptr(adreno_gpu, rptr));
/* Setup scratch/timestamp: */
- gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
+ rbmemptr(adreno_gpu, fence));
- gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
return 0;
}
@@ -180,12 +184,13 @@ int adreno_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
void adreno_flush(struct msm_gpu *gpu)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
uint32_t wptr = get_wptr(gpu->rb);
/* ensure writes to ringbuffer have hit system memory: */
mb();
- gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
}
void adreno_idle(struct msm_gpu *gpu)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 52f0515..ec84d79 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -2,6 +2,8 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -25,6 +27,94 @@
#include "adreno_common.xml.h"
#include "adreno_pm4.xml.h"
+#define REG_ADRENO_UNUSED 0xFFFFFFFF
+#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = _reg
+/**
+ * adreno_regs: List of registers that are used in across all
+ * 3D devices. Each device type has different offset value for the same
+ * register, so an array of register offsets are declared for every device
+ * and are indexed by the enumeration values defined in this enum
+ */
+enum adreno_regs {
+ REG_ADRENO_CP_DEBUG,
+ REG_ADRENO_CP_ME_RAM_WADDR,
+ REG_ADRENO_CP_ME_RAM_DATA,
+ REG_ADRENO_CP_PFP_UCODE_DATA,
+ REG_ADRENO_CP_PFP_UCODE_ADDR,
+ REG_ADRENO_CP_WFI_PEND_CTR,
+ REG_ADRENO_CP_RB_BASE,
+ REG_ADRENO_CP_RB_RPTR_ADDR,
+ REG_ADRENO_CP_RB_RPTR,
+ REG_ADRENO_CP_RB_WPTR,
+ REG_ADRENO_CP_PROTECT_CTRL,
+ REG_ADRENO_CP_ME_CNTL,
+ REG_ADRENO_CP_RB_CNTL,
+ REG_ADRENO_CP_IB1_BASE,
+ REG_ADRENO_CP_IB1_BUFSZ,
+ REG_ADRENO_CP_IB2_BASE,
+ REG_ADRENO_CP_IB2_BUFSZ,
+ REG_ADRENO_CP_TIMESTAMP,
+ REG_ADRENO_CP_ME_RAM_RADDR,
+ REG_ADRENO_CP_ROQ_ADDR,
+ REG_ADRENO_CP_ROQ_DATA,
+ REG_ADRENO_CP_MERCIU_ADDR,
+ REG_ADRENO_CP_MERCIU_DATA,
+ REG_ADRENO_CP_MERCIU_DATA2,
+ REG_ADRENO_CP_MEQ_ADDR,
+ REG_ADRENO_CP_MEQ_DATA,
+ REG_ADRENO_CP_HW_FAULT,
+ REG_ADRENO_CP_PROTECT_STATUS,
+ REG_ADRENO_SCRATCH_ADDR,
+ REG_ADRENO_SCRATCH_UMSK,
+ REG_ADRENO_SCRATCH_REG2,
+ REG_ADRENO_RBBM_STATUS,
+ REG_ADRENO_RBBM_PERFCTR_CTL,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
+ REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
+ REG_ADRENO_RBBM_INT_0_MASK,
+ REG_ADRENO_RBBM_INT_0_STATUS,
+ REG_ADRENO_RBBM_AHB_ERROR_STATUS,
+ REG_ADRENO_RBBM_PM_OVERRIDE2,
+ REG_ADRENO_RBBM_AHB_CMD,
+ REG_ADRENO_RBBM_INT_CLEAR_CMD,
+ REG_ADRENO_RBBM_SW_RESET_CMD,
+ REG_ADRENO_RBBM_CLOCK_CTL,
+ REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
+ REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
+ REG_ADRENO_VPC_DEBUG_RAM_SEL,
+ REG_ADRENO_VPC_DEBUG_RAM_READ,
+ REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
+ REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
+ REG_ADRENO_VSC_SIZE_ADDRESS,
+ REG_ADRENO_VFD_CONTROL_0,
+ REG_ADRENO_VFD_FETCH_INSTR_0_0,
+ REG_ADRENO_VFD_FETCH_INSTR_1_F,
+ REG_ADRENO_VFD_INDEX_MAX,
+ REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
+ REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
+ REG_ADRENO_SP_VS_OBJ_START_REG,
+ REG_ADRENO_SP_FS_OBJ_START_REG,
+ REG_ADRENO_PA_SC_AA_CONFIG,
+ REG_ADRENO_SQ_GPR_MANAGEMENT,
+ REG_ADRENO_SQ_INST_STORE_MANAGMENT,
+ REG_ADRENO_TP0_CHICKEN,
+ REG_ADRENO_RBBM_RBBM_CTL,
+ REG_ADRENO_UCHE_INVALIDATE0,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
+ REG_ADRENO_REGISTER_MAX,
+};
+
+/**
+ * adreno_reg_offsets: Holds array of register offsets
+ * @offsets: Offset array of size defined by enum adreno_regs
+ */
+struct adreno_reg_offsets {
+ unsigned int *const offsets;
+};
+
struct adreno_rev {
uint8_t core;
uint8_t major;
@@ -76,6 +166,13 @@ struct adreno_gpu {
struct adreno_rbmemptrs *memptrs;
struct drm_gem_object *memptrs_bo;
uint32_t memptrs_iova;
+
+ /*
+ * Register offsets are different between some GPUs.
+ * GPU specific offsets will be exported by GPU specific
+ * code (a3xx_gpu.c) and stored in this common location.
+ */
+ const struct adreno_reg_offsets *reg_offsets;
};
#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
@@ -171,5 +268,38 @@ OUT_PKT3(struct msm_ringbuffer *ring, uint8_t
opcode, uint16_t cnt)
OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
}
+/*
+ * adreno_checkreg_off() - Checks the validity of a register enum
+ * @gpu: Pointer to struct adreno_gpu
+ * @offset_name: The register enum that is checked
+ */
+static inline bool adreno_reg_check(struct adreno_gpu *gpu,
+ enum adreno_regs offset_name)
+{
+ if (offset_name >= REG_ADRENO_REGISTER_MAX ||
+ REG_ADRENO_UNUSED ==
+ gpu->reg_offsets->offsets[offset_name]) {
+ BUG();
+ }
+ return true;
+}
+
+static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
+ enum adreno_regs offset_name)
+{
+ u32 reg = gpu->reg_offsets->offsets[offset_name];
+ u32 val = 0;
+ if(adreno_reg_check(gpu,offset_name))
+ val = gpu_read(&gpu->base,reg);
+ return val;
+}
+
+static inline void adreno_gpu_write(struct adreno_gpu *gpu,
+ enum adreno_regs offset_name, u32 data)
+{
+ u32 reg = gpu->reg_offsets->offsets[offset_name];
+ if(adreno_reg_check(gpu, offset_name))
+ gpu_write(&gpu->base, reg, data);
+}
#endif /* __ADRENO_GPU_H__ */
--
1.8.5.2
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx
2014-10-31 2:33 [PATCH 0/3] drm/msm: Adreno 4xx support Ganesan, Aravind
@ 2014-10-31 15:08 ` Ganesan, Aravind
2014-11-06 21:11 ` Rob Clark
0 siblings, 1 reply; 4+ messages in thread
From: Ganesan, Aravind @ 2014-10-31 15:08 UTC (permalink / raw)
To: freedreno, Rob Clark; +Cc: dri-devel, linux-arm-msm, Jordan Crouse, rishib
Register offsets have changed between a3xx and a4xx GPUs.
To be able access these registers in common code, we create
a lookup table, and set of read-write APIs to access the
register through the lookup table.
Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org>
---
Resend the patch-set with the same thread-id
Resend in patch-set format and with dri-devel@lists.freedesktop.org on
the CC.
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 103 +++++++++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++--
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130
++++++++++++++++++++++++++++++++
3 files changed, 244 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 6c4a91a..9713aef9 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -2,6 +2,8 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
gpu_read(gpu, REG_A3XX_RBBM_STATUS));
adreno_dump(gpu);
}
+/* Register offset defines for A3XX */
+static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
+ REG_A3XX_CP_PFP_UCODE_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
+ REG_A3XX_CP_PFP_UCODE_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
+ REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
+ REG_A3XX_CP_PROTECT_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
+ REG_A3XX_RBBM_PERFCTR_CTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
+ REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
+ REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
+ REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
+ REG_A3XX_RBBM_INT_0_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
+ REG_A3XX_RBBM_AHB_ERROR_STATUS),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,
+ REG_A3XX_RBBM_INT_CLEAR_CMD),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,
+ REG_A3XX_VPC_VPC_DEBUG_RAM_SEL),
+ REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ,
+ REG_A3XX_VPC_VPC_DEBUG_RAM_READ),
+ REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
+ REG_A3XX_VSC_PIPE_DATA_ADDRESS_0),
+ REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
+ REG_A3XX_VSC_PIPE_DATA_LENGTH_7),
+ REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS,
+ REG_A3XX_VSC_SIZE_ADDRESS),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_0_0,
+ REG_A3XX_VFD_FETCH_INSTR_0_0),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_1_F,
+ REG_A3XX_VFD_FETCH_INSTR_1_F),
+ REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
+ REG_A3XX_SP_VS_PVT_MEM_ADDR_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
+ REG_A3XX_SP_FS_PVT_MEM_ADDR_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG,
+ REG_A3XX_SP_VS_OBJ_START_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG,
+ REG_A3XX_SP_FS_OBJ_START_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2,
+ REG_A3XX_RBBM_PM_OVERRIDE2),
+ REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2),
+ REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT,
+ REG_A3XX_SQ_GPR_MANAGEMENT),
+ REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT,
+ REG_A3XX_SQ_INST_STORE_MANAGMENT),
+ REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD,
+ REG_A3XX_RBBM_SW_RESET_CMD),
+ REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0,
+ REG_A3XX_UCHE_CACHE_INVALIDATE0_REG),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
+ REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO),
+ REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
+ REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI),
+};
+
+static const struct adreno_reg_offsets reg_offsets = {
+ .offsets = a3xx_register_offsets,
+};
static const struct adreno_gpu_funcs funcs = {
.base = {
@@ -461,6 +563,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
adreno_gpu->registers = a3xx_registers;
+ adreno_gpu->reg_offsets = ®_offsets;
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
if (ret)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index a74794b..82619b1 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -2,6 +2,8 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -55,19 +57,21 @@ int adreno_hw_init(struct msm_gpu *gpu)
DBG("%s", gpu->name);
/* Setup REG_CP_RB_CNTL: */
- gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
/* size is log2(quad-words): */
AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
/* Setup ringbuffer address: */
- gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
- gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
+ rbmemptr(adreno_gpu, rptr));
/* Setup scratch/timestamp: */
- gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
+ rbmemptr(adreno_gpu, fence));
- gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
return 0;
}
@@ -180,12 +184,13 @@ int adreno_submit(struct msm_gpu *gpu, struct
msm_gem_submit *submit,
void adreno_flush(struct msm_gpu *gpu)
{
+ struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
uint32_t wptr = get_wptr(gpu->rb);
/* ensure writes to ringbuffer have hit system memory: */
mb();
- gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
+ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
}
void adreno_idle(struct msm_gpu *gpu)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 52f0515..ec84d79 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -2,6 +2,8 @@
* Copyright (C) 2013 Red Hat
* Author: Rob Clark <robdclark@gmail.com>
*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as
published by
* the Free Software Foundation.
@@ -25,6 +27,94 @@
#include "adreno_common.xml.h"
#include "adreno_pm4.xml.h"
+#define REG_ADRENO_UNUSED 0xFFFFFFFF
+#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = _reg
+/**
+ * adreno_regs: List of registers that are used in across all
+ * 3D devices. Each device type has different offset value for the same
+ * register, so an array of register offsets are declared for every device
+ * and are indexed by the enumeration values defined in this enum
+ */
+enum adreno_regs {
+ REG_ADRENO_CP_DEBUG,
+ REG_ADRENO_CP_ME_RAM_WADDR,
+ REG_ADRENO_CP_ME_RAM_DATA,
+ REG_ADRENO_CP_PFP_UCODE_DATA,
+ REG_ADRENO_CP_PFP_UCODE_ADDR,
+ REG_ADRENO_CP_WFI_PEND_CTR,
+ REG_ADRENO_CP_RB_BASE,
+ REG_ADRENO_CP_RB_RPTR_ADDR,
+ REG_ADRENO_CP_RB_RPTR,
+ REG_ADRENO_CP_RB_WPTR,
+ REG_ADRENO_CP_PROTECT_CTRL,
+ REG_ADRENO_CP_ME_CNTL,
+ REG_ADRENO_CP_RB_CNTL,
+ REG_ADRENO_CP_IB1_BASE,
+ REG_ADRENO_CP_IB1_BUFSZ,
+ REG_ADRENO_CP_IB2_BASE,
+ REG_ADRENO_CP_IB2_BUFSZ,
+ REG_ADRENO_CP_TIMESTAMP,
+ REG_ADRENO_CP_ME_RAM_RADDR,
+ REG_ADRENO_CP_ROQ_ADDR,
+ REG_ADRENO_CP_ROQ_DATA,
+ REG_ADRENO_CP_MERCIU_ADDR,
+ REG_ADRENO_CP_MERCIU_DATA,
+ REG_ADRENO_CP_MERCIU_DATA2,
+ REG_ADRENO_CP_MEQ_ADDR,
+ REG_ADRENO_CP_MEQ_DATA,
+ REG_ADRENO_CP_HW_FAULT,
+ REG_ADRENO_CP_PROTECT_STATUS,
+ REG_ADRENO_SCRATCH_ADDR,
+ REG_ADRENO_SCRATCH_UMSK,
+ REG_ADRENO_SCRATCH_REG2,
+ REG_ADRENO_RBBM_STATUS,
+ REG_ADRENO_RBBM_PERFCTR_CTL,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
+ REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
+ REG_ADRENO_RBBM_INT_0_MASK,
+ REG_ADRENO_RBBM_INT_0_STATUS,
+ REG_ADRENO_RBBM_AHB_ERROR_STATUS,
+ REG_ADRENO_RBBM_PM_OVERRIDE2,
+ REG_ADRENO_RBBM_AHB_CMD,
+ REG_ADRENO_RBBM_INT_CLEAR_CMD,
+ REG_ADRENO_RBBM_SW_RESET_CMD,
+ REG_ADRENO_RBBM_CLOCK_CTL,
+ REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
+ REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
+ REG_ADRENO_VPC_DEBUG_RAM_SEL,
+ REG_ADRENO_VPC_DEBUG_RAM_READ,
+ REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
+ REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
+ REG_ADRENO_VSC_SIZE_ADDRESS,
+ REG_ADRENO_VFD_CONTROL_0,
+ REG_ADRENO_VFD_FETCH_INSTR_0_0,
+ REG_ADRENO_VFD_FETCH_INSTR_1_F,
+ REG_ADRENO_VFD_INDEX_MAX,
+ REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
+ REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
+ REG_ADRENO_SP_VS_OBJ_START_REG,
+ REG_ADRENO_SP_FS_OBJ_START_REG,
+ REG_ADRENO_PA_SC_AA_CONFIG,
+ REG_ADRENO_SQ_GPR_MANAGEMENT,
+ REG_ADRENO_SQ_INST_STORE_MANAGMENT,
+ REG_ADRENO_TP0_CHICKEN,
+ REG_ADRENO_RBBM_RBBM_CTL,
+ REG_ADRENO_UCHE_INVALIDATE0,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
+ REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
+ REG_ADRENO_REGISTER_MAX,
+};
+
+/**
+ * adreno_reg_offsets: Holds array of register offsets
+ * @offsets: Offset array of size defined by enum adreno_regs
+ */
+struct adreno_reg_offsets {
+ unsigned int *const offsets;
+};
+
struct adreno_rev {
uint8_t core;
uint8_t major;
@@ -76,6 +166,13 @@ struct adreno_gpu {
struct adreno_rbmemptrs *memptrs;
struct drm_gem_object *memptrs_bo;
uint32_t memptrs_iova;
+
+ /*
+ * Register offsets are different between some GPUs.
+ * GPU specific offsets will be exported by GPU specific
+ * code (a3xx_gpu.c) and stored in this common location.
+ */
+ const struct adreno_reg_offsets *reg_offsets;
};
#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
@@ -171,5 +268,38 @@ OUT_PKT3(struct msm_ringbuffer *ring, uint8_t
opcode, uint16_t cnt)
OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
}
+/*
+ * adreno_checkreg_off() - Checks the validity of a register enum
+ * @gpu: Pointer to struct adreno_gpu
+ * @offset_name: The register enum that is checked
+ */
+static inline bool adreno_reg_check(struct adreno_gpu *gpu,
+ enum adreno_regs offset_name)
+{
+ if (offset_name >= REG_ADRENO_REGISTER_MAX ||
+ REG_ADRENO_UNUSED ==
+ gpu->reg_offsets->offsets[offset_name]) {
+ BUG();
+ }
+ return true;
+}
+
+static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
+ enum adreno_regs offset_name)
+{
+ u32 reg = gpu->reg_offsets->offsets[offset_name];
+ u32 val = 0;
+ if(adreno_reg_check(gpu,offset_name))
+ val = gpu_read(&gpu->base,reg);
+ return val;
+}
+
+static inline void adreno_gpu_write(struct adreno_gpu *gpu,
+ enum adreno_regs offset_name, u32 data)
+{
+ u32 reg = gpu->reg_offsets->offsets[offset_name];
+ if(adreno_reg_check(gpu, offset_name))
+ gpu_write(&gpu->base, reg, data);
+}
#endif /* __ADRENO_GPU_H__ */
--
1.8.5.2
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx
2014-10-31 15:08 ` [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx Ganesan, Aravind
@ 2014-11-06 21:11 ` Rob Clark
2014-11-08 0:32 ` Ganesan, Aravind
0 siblings, 1 reply; 4+ messages in thread
From: Rob Clark @ 2014-11-06 21:11 UTC (permalink / raw)
To: Ganesan, Aravind
Cc: linux-arm-msm, freedreno, Rishi Bhattacharya,
dri-devel@lists.freedesktop.org
On Fri, Oct 31, 2014 at 11:08 AM, Ganesan, Aravind
<aravindg@codeaurora.org> wrote:
> Register offsets have changed between a3xx and a4xx GPUs.
> To be able access these registers in common code, we create
> a lookup table, and set of read-write APIs to access the
> register through the lookup table.
>
> Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org>
> ---
> Resend the patch-set with the same thread-id
> Resend in patch-set format and with dri-devel@lists.freedesktop.org on
> the CC.
> drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 103 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++--
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130
> ++++++++++++++++++++++++++++++++
> 3 files changed, 244 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> index 6c4a91a..9713aef9 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -2,6 +2,8 @@
> * Copyright (C) 2013 Red Hat
> * Author: Rob Clark <robdclark@gmail.com>
> *
> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
> + *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License version 2 as
> published by
> * the Free Software Foundation.
> @@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
> gpu_read(gpu, REG_A3XX_RBBM_STATUS));
> adreno_dump(gpu);
> }
> +/* Register offset defines for A3XX */
> +static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
> + REG_A3XX_CP_PFP_UCODE_DATA),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
> + REG_A3XX_CP_PFP_UCODE_ADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
> + REG_A3XX_CP_PROTECT_STATUS),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
> + REG_A3XX_RBBM_PERFCTR_CTL),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
> + REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
> + REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
> + REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
> + REG_A3XX_RBBM_INT_0_STATUS),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
> + REG_A3XX_RBBM_AHB_ERROR_STATUS),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,
> + REG_A3XX_RBBM_INT_CLEAR_CMD),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),
> + REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,
> + REG_A3XX_VPC_VPC_DEBUG_RAM_SEL),
> + REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ,
> + REG_A3XX_VPC_VPC_DEBUG_RAM_READ),
> + REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
> + REG_A3XX_VSC_PIPE_DATA_ADDRESS_0),
> + REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
> + REG_A3XX_VSC_PIPE_DATA_LENGTH_7),
> + REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS,
> + REG_A3XX_VSC_SIZE_ADDRESS),
> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0),
> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_0_0,
> + REG_A3XX_VFD_FETCH_INSTR_0_0),
> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_1_F,
> + REG_A3XX_VFD_FETCH_INSTR_1_F),
> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX),
> + REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
> + REG_A3XX_SP_VS_PVT_MEM_ADDR_REG),
> + REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
> + REG_A3XX_SP_FS_PVT_MEM_ADDR_REG),
> + REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG,
> + REG_A3XX_SP_VS_OBJ_START_REG),
> + REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG,
> + REG_A3XX_SP_FS_OBJ_START_REG),
> + REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2,
> + REG_A3XX_RBBM_PM_OVERRIDE2),
> + REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2),
> + REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT,
> + REG_A3XX_SQ_GPR_MANAGEMENT),
> + REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT,
> + REG_A3XX_SQ_INST_STORE_MANAGMENT),
> + REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD,
> + REG_A3XX_RBBM_SW_RESET_CMD),
> + REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0,
> + REG_A3XX_UCHE_CACHE_INVALIDATE0_REG),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
> + REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO),
> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
> + REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI),
> +};
> +
> +static const struct adreno_reg_offsets reg_offsets = {
> + .offsets = a3xx_register_offsets,
> +};
>
> static const struct adreno_gpu_funcs funcs = {
> .base = {
> @@ -461,6 +563,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
> gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
>
> adreno_gpu->registers = a3xx_registers;
> + adreno_gpu->reg_offsets = ®_offsets;
>
> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
> if (ret)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index a74794b..82619b1 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -2,6 +2,8 @@
> * Copyright (C) 2013 Red Hat
> * Author: Rob Clark <robdclark@gmail.com>
> *
> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
> + *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License version 2 as
> published by
> * the Free Software Foundation.
> @@ -55,19 +57,21 @@ int adreno_hw_init(struct msm_gpu *gpu)
> DBG("%s", gpu->name);
>
> /* Setup REG_CP_RB_CNTL: */
> - gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
> /* size is log2(quad-words): */
> AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
> AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
>
> /* Setup ringbuffer address: */
> - gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
> - gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
> + rbmemptr(adreno_gpu, rptr));
>
> /* Setup scratch/timestamp: */
> - gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
> + adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
> + rbmemptr(adreno_gpu, fence));
>
> - gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
> + adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
>
> return 0;
> }
> @@ -180,12 +184,13 @@ int adreno_submit(struct msm_gpu *gpu, struct
> msm_gem_submit *submit,
>
> void adreno_flush(struct msm_gpu *gpu)
> {
> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
> uint32_t wptr = get_wptr(gpu->rb);
>
> /* ensure writes to ringbuffer have hit system memory: */
> mb();
>
> - gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
> }
>
> void adreno_idle(struct msm_gpu *gpu)
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 52f0515..ec84d79 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -2,6 +2,8 @@
> * Copyright (C) 2013 Red Hat
> * Author: Rob Clark <robdclark@gmail.com>
> *
> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
> + *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License version 2 as
> published by
> * the Free Software Foundation.
> @@ -25,6 +27,94 @@
> #include "adreno_common.xml.h"
> #include "adreno_pm4.xml.h"
>
> +#define REG_ADRENO_UNUSED 0xFFFFFFFF
so, unititialized table elements will be zero, not 0xffffffff. I
think maybe it would be better to do something like:
#define REG_ADRENO_UNUSED 0xFFFFFFFF
#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
(and then subtract off the +1 in the read/write helper fxns)
Also, the extra 'struct adreno_reg_offsets' seems kinda pointless, so
I think we can drop that and just put the array ptr directly in
'struct adreno_gpu'.
BR,
-R
> +#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = _reg
> +/**
> + * adreno_regs: List of registers that are used in across all
> + * 3D devices. Each device type has different offset value for the same
> + * register, so an array of register offsets are declared for every device
> + * and are indexed by the enumeration values defined in this enum
> + */
> +enum adreno_regs {
> + REG_ADRENO_CP_DEBUG,
> + REG_ADRENO_CP_ME_RAM_WADDR,
> + REG_ADRENO_CP_ME_RAM_DATA,
> + REG_ADRENO_CP_PFP_UCODE_DATA,
> + REG_ADRENO_CP_PFP_UCODE_ADDR,
> + REG_ADRENO_CP_WFI_PEND_CTR,
> + REG_ADRENO_CP_RB_BASE,
> + REG_ADRENO_CP_RB_RPTR_ADDR,
> + REG_ADRENO_CP_RB_RPTR,
> + REG_ADRENO_CP_RB_WPTR,
> + REG_ADRENO_CP_PROTECT_CTRL,
> + REG_ADRENO_CP_ME_CNTL,
> + REG_ADRENO_CP_RB_CNTL,
> + REG_ADRENO_CP_IB1_BASE,
> + REG_ADRENO_CP_IB1_BUFSZ,
> + REG_ADRENO_CP_IB2_BASE,
> + REG_ADRENO_CP_IB2_BUFSZ,
> + REG_ADRENO_CP_TIMESTAMP,
> + REG_ADRENO_CP_ME_RAM_RADDR,
> + REG_ADRENO_CP_ROQ_ADDR,
> + REG_ADRENO_CP_ROQ_DATA,
> + REG_ADRENO_CP_MERCIU_ADDR,
> + REG_ADRENO_CP_MERCIU_DATA,
> + REG_ADRENO_CP_MERCIU_DATA2,
> + REG_ADRENO_CP_MEQ_ADDR,
> + REG_ADRENO_CP_MEQ_DATA,
> + REG_ADRENO_CP_HW_FAULT,
> + REG_ADRENO_CP_PROTECT_STATUS,
> + REG_ADRENO_SCRATCH_ADDR,
> + REG_ADRENO_SCRATCH_UMSK,
> + REG_ADRENO_SCRATCH_REG2,
> + REG_ADRENO_RBBM_STATUS,
> + REG_ADRENO_RBBM_PERFCTR_CTL,
> + REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
> + REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
> + REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
> + REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
> + REG_ADRENO_RBBM_INT_0_MASK,
> + REG_ADRENO_RBBM_INT_0_STATUS,
> + REG_ADRENO_RBBM_AHB_ERROR_STATUS,
> + REG_ADRENO_RBBM_PM_OVERRIDE2,
> + REG_ADRENO_RBBM_AHB_CMD,
> + REG_ADRENO_RBBM_INT_CLEAR_CMD,
> + REG_ADRENO_RBBM_SW_RESET_CMD,
> + REG_ADRENO_RBBM_CLOCK_CTL,
> + REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
> + REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
> + REG_ADRENO_VPC_DEBUG_RAM_SEL,
> + REG_ADRENO_VPC_DEBUG_RAM_READ,
> + REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
> + REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
> + REG_ADRENO_VSC_SIZE_ADDRESS,
> + REG_ADRENO_VFD_CONTROL_0,
> + REG_ADRENO_VFD_FETCH_INSTR_0_0,
> + REG_ADRENO_VFD_FETCH_INSTR_1_F,
> + REG_ADRENO_VFD_INDEX_MAX,
> + REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
> + REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
> + REG_ADRENO_SP_VS_OBJ_START_REG,
> + REG_ADRENO_SP_FS_OBJ_START_REG,
> + REG_ADRENO_PA_SC_AA_CONFIG,
> + REG_ADRENO_SQ_GPR_MANAGEMENT,
> + REG_ADRENO_SQ_INST_STORE_MANAGMENT,
> + REG_ADRENO_TP0_CHICKEN,
> + REG_ADRENO_RBBM_RBBM_CTL,
> + REG_ADRENO_UCHE_INVALIDATE0,
> + REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
> + REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
> + REG_ADRENO_REGISTER_MAX,
> +};
> +
> +/**
> + * adreno_reg_offsets: Holds array of register offsets
> + * @offsets: Offset array of size defined by enum adreno_regs
> + */
> +struct adreno_reg_offsets {
> + unsigned int *const offsets;
> +};
> +
> struct adreno_rev {
> uint8_t core;
> uint8_t major;
> @@ -76,6 +166,13 @@ struct adreno_gpu {
> struct adreno_rbmemptrs *memptrs;
> struct drm_gem_object *memptrs_bo;
> uint32_t memptrs_iova;
> +
> + /*
> + * Register offsets are different between some GPUs.
> + * GPU specific offsets will be exported by GPU specific
> + * code (a3xx_gpu.c) and stored in this common location.
> + */
> + const struct adreno_reg_offsets *reg_offsets;
> };
> #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
>
> @@ -171,5 +268,38 @@ OUT_PKT3(struct msm_ringbuffer *ring, uint8_t
> opcode, uint16_t cnt)
> OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
> }
>
> +/*
> + * adreno_checkreg_off() - Checks the validity of a register enum
> + * @gpu: Pointer to struct adreno_gpu
> + * @offset_name: The register enum that is checked
> + */
> +static inline bool adreno_reg_check(struct adreno_gpu *gpu,
> + enum adreno_regs offset_name)
> +{
> + if (offset_name >= REG_ADRENO_REGISTER_MAX ||
> + REG_ADRENO_UNUSED ==
> + gpu->reg_offsets->offsets[offset_name]) {
> + BUG();
> + }
> + return true;
> +}
> +
> +static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
> + enum adreno_regs offset_name)
> +{
> + u32 reg = gpu->reg_offsets->offsets[offset_name];
> + u32 val = 0;
> + if(adreno_reg_check(gpu,offset_name))
> + val = gpu_read(&gpu->base,reg);
> + return val;
> +}
> +
> +static inline void adreno_gpu_write(struct adreno_gpu *gpu,
> + enum adreno_regs offset_name, u32 data)
> +{
> + u32 reg = gpu->reg_offsets->offsets[offset_name];
> + if(adreno_reg_check(gpu, offset_name))
> + gpu_write(&gpu->base, reg, data);
> +}
>
> #endif /* __ADRENO_GPU_H__ */
> --
> 1.8.5.2
>
> --
> Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx
2014-11-06 21:11 ` Rob Clark
@ 2014-11-08 0:32 ` Ganesan, Aravind
0 siblings, 0 replies; 4+ messages in thread
From: Ganesan, Aravind @ 2014-11-08 0:32 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, freedreno, Rishi Bhattacharya,
dri-devel@lists.freedesktop.org
On 11/6/2014 2:11 PM, Rob Clark wrote:
> On Fri, Oct 31, 2014 at 11:08 AM, Ganesan, Aravind
> <aravindg@codeaurora.org> wrote:
>> Register offsets have changed between a3xx and a4xx GPUs.
>> To be able access these registers in common code, we create
>> a lookup table, and set of read-write APIs to access the
>> register through the lookup table.
>>
>> Signed-off-by: Aravind Ganesan <aravindg@codeaurora.org>
>> ---
>> Resend the patch-set with the same thread-id
>> Resend in patch-set format and with dri-devel@lists.freedesktop.org on
>> the CC.
>> drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 103 +++++++++++++++++++++++++
>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 17 +++--
>> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 130
>> ++++++++++++++++++++++++++++++++
>> 3 files changed, 244 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> index 6c4a91a..9713aef9 100644
>> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
>> @@ -2,6 +2,8 @@
>> * Copyright (C) 2013 Red Hat
>> * Author: Rob Clark <robdclark@gmail.com>
>> *
>> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
>> + *
>> * This program is free software; you can redistribute it and/or modify it
>> * under the terms of the GNU General Public License version 2 as
>> published by
>> * the Free Software Foundation.
>> @@ -404,6 +406,106 @@ static void a3xx_dump(struct msm_gpu *gpu)
>> gpu_read(gpu, REG_A3XX_RBBM_STATUS));
>> adreno_dump(gpu);
>> }
>> +/* Register offset defines for A3XX */
>> +static unsigned int a3xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_DEBUG, REG_AXXX_CP_DEBUG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_WADDR, REG_AXXX_CP_ME_RAM_WADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_DATA, REG_AXXX_CP_ME_RAM_DATA),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_DATA,
>> + REG_A3XX_CP_PFP_UCODE_DATA),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PFP_UCODE_ADDR,
>> + REG_A3XX_CP_PFP_UCODE_ADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_WFI_PEND_CTR, REG_A3XX_CP_WFI_PEND_CTR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR_ADDR, REG_AXXX_CP_RB_RPTR_ADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_RPTR, REG_AXXX_CP_RB_RPTR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_WPTR, REG_AXXX_CP_RB_WPTR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_CTRL, REG_A3XX_CP_PROTECT_CTRL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_CNTL, REG_AXXX_CP_ME_CNTL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_AXXX_CP_RB_CNTL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BASE, REG_A3XX_CP_IB1_BASE),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB1_BUFSZ, REG_A3XX_CP_IB1_BUFSZ),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BASE, REG_A3XX_CP_IB2_BASE),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_IB2_BUFSZ, REG_A3XX_CP_IB2_BUFSZ),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_TIMESTAMP, REG_AXXX_CP_SCRATCH_REG0),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ME_RAM_RADDR, REG_AXXX_CP_ME_RAM_RADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_ADDR, REG_AXXX_SCRATCH_ADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_UMSK, REG_AXXX_SCRATCH_UMSK),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_ADDR, REG_A3XX_CP_ROQ_ADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_ROQ_DATA, REG_A3XX_CP_ROQ_DATA),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_ADDR, REG_A3XX_CP_MERCIU_ADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA, REG_A3XX_CP_MERCIU_DATA),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MERCIU_DATA2, REG_A3XX_CP_MERCIU_DATA2),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_ADDR, REG_A3XX_CP_MEQ_ADDR),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_MEQ_DATA, REG_A3XX_CP_MEQ_DATA),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_HW_FAULT, REG_A3XX_CP_HW_FAULT),
>> + REG_ADRENO_DEFINE(REG_ADRENO_CP_PROTECT_STATUS,
>> + REG_A3XX_CP_PROTECT_STATUS),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_STATUS, REG_A3XX_RBBM_STATUS),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_CTL,
>> + REG_A3XX_RBBM_PERFCTR_CTL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
>> + REG_A3XX_RBBM_PERFCTR_LOAD_CMD0),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
>> + REG_A3XX_RBBM_PERFCTR_LOAD_CMD1),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
>> + REG_A3XX_RBBM_PERFCTR_PWR_1_LO),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_MASK, REG_A3XX_RBBM_INT_0_MASK),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_0_STATUS,
>> + REG_A3XX_RBBM_INT_0_STATUS),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_ERROR_STATUS,
>> + REG_A3XX_RBBM_AHB_ERROR_STATUS),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_AHB_CMD, REG_A3XX_RBBM_AHB_CMD),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_INT_CLEAR_CMD,
>> + REG_A3XX_RBBM_INT_CLEAR_CMD),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_CLOCK_CTL, REG_A3XX_RBBM_CLOCK_CTL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_SEL,
>> + REG_A3XX_VPC_VPC_DEBUG_RAM_SEL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VPC_DEBUG_RAM_READ,
>> + REG_A3XX_VPC_VPC_DEBUG_RAM_READ),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
>> + REG_A3XX_VSC_PIPE_DATA_ADDRESS_0),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
>> + REG_A3XX_VSC_PIPE_DATA_LENGTH_7),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VSC_SIZE_ADDRESS,
>> + REG_A3XX_VSC_SIZE_ADDRESS),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_CONTROL_0, REG_A3XX_VFD_CONTROL_0),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_0_0,
>> + REG_A3XX_VFD_FETCH_INSTR_0_0),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_FETCH_INSTR_1_F,
>> + REG_A3XX_VFD_FETCH_INSTR_1_F),
>> + REG_ADRENO_DEFINE(REG_ADRENO_VFD_INDEX_MAX, REG_A3XX_VFD_INDEX_MAX),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
>> + REG_A3XX_SP_VS_PVT_MEM_ADDR_REG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
>> + REG_A3XX_SP_FS_PVT_MEM_ADDR_REG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SP_VS_OBJ_START_REG,
>> + REG_A3XX_SP_VS_OBJ_START_REG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SP_FS_OBJ_START_REG,
>> + REG_A3XX_SP_FS_OBJ_START_REG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_PA_SC_AA_CONFIG, REG_A3XX_PA_SC_AA_CONFIG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PM_OVERRIDE2,
>> + REG_A3XX_RBBM_PM_OVERRIDE2),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SCRATCH_REG2, REG_AXXX_CP_SCRATCH_REG2),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SQ_GPR_MANAGEMENT,
>> + REG_A3XX_SQ_GPR_MANAGEMENT),
>> + REG_ADRENO_DEFINE(REG_ADRENO_SQ_INST_STORE_MANAGMENT,
>> + REG_A3XX_SQ_INST_STORE_MANAGMENT),
>> + REG_ADRENO_DEFINE(REG_ADRENO_TP0_CHICKEN, REG_A3XX_TP0_CHICKEN),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_RBBM_CTL, REG_A3XX_RBBM_RBBM_CTL),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_SW_RESET_CMD,
>> + REG_A3XX_RBBM_SW_RESET_CMD),
>> + REG_ADRENO_DEFINE(REG_ADRENO_UCHE_INVALIDATE0,
>> + REG_A3XX_UCHE_CACHE_INVALIDATE0_REG),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
>> + REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO),
>> + REG_ADRENO_DEFINE(REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
>> + REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI),
>> +};
>> +
>> +static const struct adreno_reg_offsets reg_offsets = {
>> + .offsets = a3xx_register_offsets,
>> +};
>>
>> static const struct adreno_gpu_funcs funcs = {
>> .base = {
>> @@ -461,6 +563,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
>> gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
>>
>> adreno_gpu->registers = a3xx_registers;
>> + adreno_gpu->reg_offsets = ®_offsets;
>>
>> ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
>> if (ret)
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> index a74794b..82619b1 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
>> @@ -2,6 +2,8 @@
>> * Copyright (C) 2013 Red Hat
>> * Author: Rob Clark <robdclark@gmail.com>
>> *
>> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
>> + *
>> * This program is free software; you can redistribute it and/or modify it
>> * under the terms of the GNU General Public License version 2 as
>> published by
>> * the Free Software Foundation.
>> @@ -55,19 +57,21 @@ int adreno_hw_init(struct msm_gpu *gpu)
>> DBG("%s", gpu->name);
>>
>> /* Setup REG_CP_RB_CNTL: */
>> - gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
>> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
>> /* size is log2(quad-words): */
>> AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
>> AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)));
>>
>> /* Setup ringbuffer address: */
>> - gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
>> - gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
>> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
>> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
>> + rbmemptr(adreno_gpu, rptr));
>>
>> /* Setup scratch/timestamp: */
>> - gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
>> + adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR,
>> + rbmemptr(adreno_gpu, fence));
>>
>> - gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
>> + adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1);
>>
>> return 0;
>> }
>> @@ -180,12 +184,13 @@ int adreno_submit(struct msm_gpu *gpu, struct
>> msm_gem_submit *submit,
>>
>> void adreno_flush(struct msm_gpu *gpu)
>> {
>> + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
>> uint32_t wptr = get_wptr(gpu->rb);
>>
>> /* ensure writes to ringbuffer have hit system memory: */
>> mb();
>>
>> - gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
>> + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
>> }
>>
>> void adreno_idle(struct msm_gpu *gpu)
>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> index 52f0515..ec84d79 100644
>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
>> @@ -2,6 +2,8 @@
>> * Copyright (C) 2013 Red Hat
>> * Author: Rob Clark <robdclark@gmail.com>
>> *
>> + * Copyright (c) 2014 The Linux Foundation. All rights reserved.
>> + *
>> * This program is free software; you can redistribute it and/or modify it
>> * under the terms of the GNU General Public License version 2 as
>> published by
>> * the Free Software Foundation.
>> @@ -25,6 +27,94 @@
>> #include "adreno_common.xml.h"
>> #include "adreno_pm4.xml.h"
>>
>> +#define REG_ADRENO_UNUSED 0xFFFFFFFF
>
> so, unititialized table elements will be zero, not 0xffffffff. I
> think maybe it would be better to do something like:
>
> #define REG_ADRENO_UNUSED 0xFFFFFFFF
> #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
>
> (and then subtract off the +1 in the read/write helper fxns)
>
> Also, the extra 'struct adreno_reg_offsets' seems kinda pointless, so
> I think we can drop that and just put the array ptr directly in
> 'struct adreno_gpu'.
>
> BR,
> -R
Agreed.
>
>> +#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = _reg
>> +/**
>> + * adreno_regs: List of registers that are used in across all
>> + * 3D devices. Each device type has different offset value for the same
>> + * register, so an array of register offsets are declared for every device
>> + * and are indexed by the enumeration values defined in this enum
>> + */
>> +enum adreno_regs {
>> + REG_ADRENO_CP_DEBUG,
>> + REG_ADRENO_CP_ME_RAM_WADDR,
>> + REG_ADRENO_CP_ME_RAM_DATA,
>> + REG_ADRENO_CP_PFP_UCODE_DATA,
>> + REG_ADRENO_CP_PFP_UCODE_ADDR,
>> + REG_ADRENO_CP_WFI_PEND_CTR,
>> + REG_ADRENO_CP_RB_BASE,
>> + REG_ADRENO_CP_RB_RPTR_ADDR,
>> + REG_ADRENO_CP_RB_RPTR,
>> + REG_ADRENO_CP_RB_WPTR,
>> + REG_ADRENO_CP_PROTECT_CTRL,
>> + REG_ADRENO_CP_ME_CNTL,
>> + REG_ADRENO_CP_RB_CNTL,
>> + REG_ADRENO_CP_IB1_BASE,
>> + REG_ADRENO_CP_IB1_BUFSZ,
>> + REG_ADRENO_CP_IB2_BASE,
>> + REG_ADRENO_CP_IB2_BUFSZ,
>> + REG_ADRENO_CP_TIMESTAMP,
>> + REG_ADRENO_CP_ME_RAM_RADDR,
>> + REG_ADRENO_CP_ROQ_ADDR,
>> + REG_ADRENO_CP_ROQ_DATA,
>> + REG_ADRENO_CP_MERCIU_ADDR,
>> + REG_ADRENO_CP_MERCIU_DATA,
>> + REG_ADRENO_CP_MERCIU_DATA2,
>> + REG_ADRENO_CP_MEQ_ADDR,
>> + REG_ADRENO_CP_MEQ_DATA,
>> + REG_ADRENO_CP_HW_FAULT,
>> + REG_ADRENO_CP_PROTECT_STATUS,
>> + REG_ADRENO_SCRATCH_ADDR,
>> + REG_ADRENO_SCRATCH_UMSK,
>> + REG_ADRENO_SCRATCH_REG2,
>> + REG_ADRENO_RBBM_STATUS,
>> + REG_ADRENO_RBBM_PERFCTR_CTL,
>> + REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
>> + REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
>> + REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
>> + REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
>> + REG_ADRENO_RBBM_INT_0_MASK,
>> + REG_ADRENO_RBBM_INT_0_STATUS,
>> + REG_ADRENO_RBBM_AHB_ERROR_STATUS,
>> + REG_ADRENO_RBBM_PM_OVERRIDE2,
>> + REG_ADRENO_RBBM_AHB_CMD,
>> + REG_ADRENO_RBBM_INT_CLEAR_CMD,
>> + REG_ADRENO_RBBM_SW_RESET_CMD,
>> + REG_ADRENO_RBBM_CLOCK_CTL,
>> + REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
>> + REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
>> + REG_ADRENO_VPC_DEBUG_RAM_SEL,
>> + REG_ADRENO_VPC_DEBUG_RAM_READ,
>> + REG_ADRENO_VSC_PIPE_DATA_ADDRESS_0,
>> + REG_ADRENO_VSC_PIPE_DATA_LENGTH_7,
>> + REG_ADRENO_VSC_SIZE_ADDRESS,
>> + REG_ADRENO_VFD_CONTROL_0,
>> + REG_ADRENO_VFD_FETCH_INSTR_0_0,
>> + REG_ADRENO_VFD_FETCH_INSTR_1_F,
>> + REG_ADRENO_VFD_INDEX_MAX,
>> + REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
>> + REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
>> + REG_ADRENO_SP_VS_OBJ_START_REG,
>> + REG_ADRENO_SP_FS_OBJ_START_REG,
>> + REG_ADRENO_PA_SC_AA_CONFIG,
>> + REG_ADRENO_SQ_GPR_MANAGEMENT,
>> + REG_ADRENO_SQ_INST_STORE_MANAGMENT,
>> + REG_ADRENO_TP0_CHICKEN,
>> + REG_ADRENO_RBBM_RBBM_CTL,
>> + REG_ADRENO_UCHE_INVALIDATE0,
>> + REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
>> + REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
>> + REG_ADRENO_REGISTER_MAX,
>> +};
>> +
>> +/**
>> + * adreno_reg_offsets: Holds array of register offsets
>> + * @offsets: Offset array of size defined by enum adreno_regs
>> + */
>> +struct adreno_reg_offsets {
>> + unsigned int *const offsets;
>> +};
>> +
>> struct adreno_rev {
>> uint8_t core;
>> uint8_t major;
>> @@ -76,6 +166,13 @@ struct adreno_gpu {
>> struct adreno_rbmemptrs *memptrs;
>> struct drm_gem_object *memptrs_bo;
>> uint32_t memptrs_iova;
>> +
>> + /*
>> + * Register offsets are different between some GPUs.
>> + * GPU specific offsets will be exported by GPU specific
>> + * code (a3xx_gpu.c) and stored in this common location.
>> + */
>> + const struct adreno_reg_offsets *reg_offsets;
>> };
>> #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
>>
>> @@ -171,5 +268,38 @@ OUT_PKT3(struct msm_ringbuffer *ring, uint8_t
>> opcode, uint16_t cnt)
>> OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
>> }
>>
>> +/*
>> + * adreno_checkreg_off() - Checks the validity of a register enum
>> + * @gpu: Pointer to struct adreno_gpu
>> + * @offset_name: The register enum that is checked
>> + */
>> +static inline bool adreno_reg_check(struct adreno_gpu *gpu,
>> + enum adreno_regs offset_name)
>> +{
>> + if (offset_name >= REG_ADRENO_REGISTER_MAX ||
>> + REG_ADRENO_UNUSED ==
>> + gpu->reg_offsets->offsets[offset_name]) {
>> + BUG();
>> + }
>> + return true;
>> +}
>> +
>> +static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
>> + enum adreno_regs offset_name)
>> +{
>> + u32 reg = gpu->reg_offsets->offsets[offset_name];
>> + u32 val = 0;
>> + if(adreno_reg_check(gpu,offset_name))
>> + val = gpu_read(&gpu->base,reg);
>> + return val;
>> +}
>> +
>> +static inline void adreno_gpu_write(struct adreno_gpu *gpu,
>> + enum adreno_regs offset_name, u32 data)
>> +{
>> + u32 reg = gpu->reg_offsets->offsets[offset_name];
>> + if(adreno_reg_check(gpu, offset_name))
>> + gpu_write(&gpu->base, reg, data);
>> +}
>>
>> #endif /* __ADRENO_GPU_H__ */
>> --
>> 1.8.5.2
>>
>> --
>> Qualcomm Innovation Center, Inc.
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 4+ messages in thread
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Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2014-10-31 2:33 [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx Ganesan, Aravind
-- strict thread matches above, loose matches on Subject: below --
2014-10-31 2:33 [PATCH 0/3] drm/msm: Adreno 4xx support Ganesan, Aravind
2014-10-31 15:08 ` [PATCH 2/3] drm/msm: Handle register offset differences between a3xx, and a4xx Ganesan, Aravind
2014-11-06 21:11 ` Rob Clark
2014-11-08 0:32 ` Ganesan, Aravind
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