Re: [Qemu-devel] [PATCH v3 10/19] target-mips: add MSA I5 format instruction

[Leon Alrae <leon.alrae@imgtec.com>]

Hi Yongbok,

On 01/11/14 05:28, Yongbok Kim wrote:
> +    TCGv_i32 timm = tcg_temp_new_i32();
> +    tcg_gen_movi_i32(timm, u5);
> +
> +    switch (MASK_MSA_I5(ctx->opcode)) {
> +    case OPC_ADDVI_df:
> +        gen_helper_msa_addvi_df(cpu_env, tdf, twd, tws, timm);
> +        break;
> +    case OPC_SUBVI_df:
> +        gen_helper_msa_subvi_df(cpu_env, tdf, twd, tws, timm);
> +        break;
> +    case OPC_MAXI_S_df:
> +        tcg_gen_movi_i32(timm, s5);
> +        gen_helper_msa_maxi_s_df(cpu_env, tdf, twd, tws, timm);

I think tcg_gen_movi_i32(timm, u5) shouldn't be in front of the switch,
this operation is useless for instructions having signed immediate.
Probably it's not a big deal as tcg will optimize it out, but it needs
to be corrected at some point (the same applies to the 3RF group
introduced in patch #14). Otherwise,

Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>