From: "Chen, Tiejun" <tiejun.chen@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>
Cc: "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [Xen-devel] [PATCH 2/2] xen:i386:pc_piix: create isa bridge specific to IGD passthrough
Date: Mon, 03 Nov 2014 19:36:44 +0800 [thread overview]
Message-ID: <545768CC.3000903@intel.com> (raw)
In-Reply-To: <5457686E.7020601@redhat.com>
On 2014/11/3 19:35, Paolo Bonzini wrote:
> On 03/11/2014 08:48, Chen, Tiejun wrote:
>>>>>> I think the point was mostly to reserve 1f to prevent
>>>>>> devices from using it.
>>>>>> As we populate slots in order it doesn't seem to important ...
>>>>>
>>>>> If we populate slot at !1f GFX driver can't find this ISA bridge.
>>>>
>>>> Right, but I mean if no special options are used, 1f will typically
>>>> stay free without any effort on our side.
>>>
>>> Yeah.
>>>
>>> Actually based on current info we know, seems 1f is just specific to our
>>> scenario :) So I always think we can occupy that. But Paolo and you can
>>> really determine this point.
>>
>> What's your idea?
>
> I do not have any objection to always occupying 1f for Xen IGD passthrough.
>
Cool ;-)
Thanks
Tiejun
WARNING: multiple messages have this Message-ID (diff)
From: "Chen, Tiejun" <tiejun.chen@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>
Cc: "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Subject: Re: [Xen-devel] [PATCH 2/2] xen:i386:pc_piix: create isa bridge specific to IGD passthrough
Date: Mon, 03 Nov 2014 19:36:44 +0800 [thread overview]
Message-ID: <545768CC.3000903@intel.com> (raw)
In-Reply-To: <5457686E.7020601@redhat.com>
On 2014/11/3 19:35, Paolo Bonzini wrote:
> On 03/11/2014 08:48, Chen, Tiejun wrote:
>>>>>> I think the point was mostly to reserve 1f to prevent
>>>>>> devices from using it.
>>>>>> As we populate slots in order it doesn't seem to important ...
>>>>>
>>>>> If we populate slot at !1f GFX driver can't find this ISA bridge.
>>>>
>>>> Right, but I mean if no special options are used, 1f will typically
>>>> stay free without any effort on our side.
>>>
>>> Yeah.
>>>
>>> Actually based on current info we know, seems 1f is just specific to our
>>> scenario :) So I always think we can occupy that. But Paolo and you can
>>> really determine this point.
>>
>> What's your idea?
>
> I do not have any objection to always occupying 1f for Xen IGD passthrough.
>
Cool ;-)
Thanks
Tiejun
next prev parent reply other threads:[~2014-11-03 11:36 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-21 1:28 [Qemu-devel] [PATCH 0/2] qemu:xen: implement isa bridge specific to IGD passthrough Tiejun Chen
2014-08-21 1:28 ` Tiejun Chen
2014-08-21 1:28 ` [Qemu-devel] [PATCH 1/2] hw:xen:xen_pt: register " Tiejun Chen
2014-08-21 1:28 ` Tiejun Chen
2014-08-21 1:28 ` [Qemu-devel] [PATCH 2/2] xen:i386:pc_piix: create " Tiejun Chen
2014-08-21 1:28 ` Tiejun Chen
2014-08-21 16:16 ` [Qemu-devel] [Xen-devel] " Konrad Rzeszutek Wilk
2014-08-21 16:16 ` Konrad Rzeszutek Wilk
2014-08-22 1:06 ` [Qemu-devel] " Chen, Tiejun
2014-08-22 1:06 ` Chen, Tiejun
2014-08-24 11:12 ` [Qemu-devel] " Michael S. Tsirkin
2014-08-24 11:12 ` Michael S. Tsirkin
2014-08-25 5:18 ` [Qemu-devel] " Chen, Tiejun
2014-08-25 5:18 ` Chen, Tiejun
2014-08-26 2:49 ` [Qemu-devel] " Chen, Tiejun
2014-08-26 2:49 ` Chen, Tiejun
2014-08-28 0:56 ` [Qemu-devel] " Chen, Tiejun
2014-08-28 0:56 ` Chen, Tiejun
2014-08-29 1:28 ` [Qemu-devel] " Chen, Tiejun
2014-08-29 1:28 ` Chen, Tiejun
2014-08-31 8:58 ` [Qemu-devel] " Michael S. Tsirkin
2014-08-31 8:58 ` Michael S. Tsirkin
2014-09-01 2:50 ` [Qemu-devel] " Chen, Tiejun
2014-09-01 2:50 ` Chen, Tiejun
2014-09-01 6:05 ` [Qemu-devel] " Michael S. Tsirkin
2014-09-01 6:05 ` Michael S. Tsirkin
2014-09-01 7:49 ` [Qemu-devel] " Chen, Tiejun
2014-09-01 7:49 ` Chen, Tiejun
2014-09-03 1:40 ` [Qemu-devel] " Kay, Allen M
2014-09-03 1:40 ` Kay, Allen M
2014-09-03 6:27 ` [Qemu-devel] " Michael S. Tsirkin
2014-09-03 6:27 ` Michael S. Tsirkin
2014-09-03 15:06 ` [Qemu-devel] " Kay, Allen M
2014-09-03 15:06 ` Kay, Allen M
2014-09-28 2:59 ` [Qemu-devel] " Chen, Tiejun
2014-09-28 2:59 ` Chen, Tiejun
2014-09-28 5:38 ` [Qemu-devel] " Chen, Tiejun
2014-09-28 5:38 ` Chen, Tiejun
2014-10-07 7:27 ` [Qemu-devel] " Michael S. Tsirkin
2014-10-07 7:27 ` Michael S. Tsirkin
2014-10-09 2:16 ` [Qemu-devel] " Chen, Tiejun
2014-10-09 2:16 ` Chen, Tiejun
2014-09-29 10:01 ` [Qemu-devel] " Michael S. Tsirkin
2014-09-29 10:01 ` Michael S. Tsirkin
2014-09-30 2:43 ` [Qemu-devel] " Chen, Tiejun
2014-09-30 2:43 ` Chen, Tiejun
2014-10-07 1:02 ` [Qemu-devel] " Chen, Tiejun
2014-10-07 1:02 ` Chen, Tiejun
2014-10-07 7:26 ` [Qemu-devel] " Michael S. Tsirkin
2014-10-07 7:26 ` Michael S. Tsirkin
2014-10-09 5:53 ` [Qemu-devel] " Chen, Tiejun
2014-10-09 5:53 ` Chen, Tiejun
2014-10-12 9:50 ` [Qemu-devel] " Michael S. Tsirkin
2014-10-12 9:50 ` Michael S. Tsirkin
2014-10-24 7:36 ` [Qemu-devel] " Chen, Tiejun
2014-10-24 7:36 ` Chen, Tiejun
2014-10-24 13:47 ` [Qemu-devel] " Michael S. Tsirkin
2014-10-24 13:47 ` Michael S. Tsirkin
2014-10-30 7:47 ` [Qemu-devel] " Chen, Tiejun
2014-10-30 7:47 ` Chen, Tiejun
2014-11-03 7:48 ` [Qemu-devel] " Chen, Tiejun
2014-11-03 7:48 ` Chen, Tiejun
2014-11-03 11:35 ` [Qemu-devel] " Paolo Bonzini
2014-11-03 11:35 ` Paolo Bonzini
2014-11-03 11:36 ` Chen, Tiejun [this message]
2014-11-03 11:36 ` Chen, Tiejun
2014-11-03 11:47 ` [Qemu-devel] " Chen, Tiejun
2014-11-03 11:47 ` Chen, Tiejun
2014-11-03 12:01 ` [Qemu-devel] " Paolo Bonzini
2014-11-03 12:01 ` Paolo Bonzini
2014-11-03 13:10 ` [Qemu-devel] [Xen-devel] " Michael S. Tsirkin
2014-11-03 13:10 ` Michael S. Tsirkin
2014-11-05 7:23 ` [Qemu-devel] " Chen, Tiejun
2014-11-05 7:23 ` Chen, Tiejun
2014-08-22 18:23 ` [Qemu-devel] " Michael S. Tsirkin
2014-08-22 18:23 ` Michael S. Tsirkin
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