* [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board
@ 2014-10-31 12:14 Hyungwon Hwang
2014-10-31 12:14 ` [U-Boot] [PATCH v2 1/4] exynos5: fix GPIO information of exynos5420 Hyungwon Hwang
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Hyungwon Hwang @ 2014-10-31 12:14 UTC (permalink / raw)
To: u-boot
This patchset adds support for Exynos5422 odroid xu3 board.
I have done this work on the patchset submitted by Akshay Saraswat.
https://patchwork.ozlabs.org/patch/400043/
Hyungwon Hwang (4):
exynos5: fix GPIO information of exynos5420
Exynos5800: Add support for Exynos5800
odroid: make some macros common
Odroid-XU3: Add support for Odroid-XU3
arch/arm/cpu/armv7/exynos/Kconfig | 4 +
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 72 +++++++++
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 261 +++++++++++++++++---------------
board/samsung/odroid-xu3/Kconfig | 12 ++
board/samsung/odroid-xu3/MAINTAINERS | 6 +
board/samsung/odroid-xu3/Makefile | 7 +
board/samsung/odroid-xu3/odroid-xu3.c | 132 ++++++++++++++++
board/samsung/odroid-xu3/setup.h | 115 ++++++++++++++
board/samsung/odroid/odroid.c | 1 +
board/samsung/odroid/setup.h | 8 -
configs/odroid-xu3_defconfig | 4 +
drivers/gpio/s5p_gpio.c | 4 +-
include/configs/odroid_xu3.h | 73 +++++++++
15 files changed, 576 insertions(+), 137 deletions(-)
create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
create mode 100644 board/samsung/odroid-xu3/Kconfig
create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
create mode 100644 board/samsung/odroid-xu3/Makefile
create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
create mode 100644 board/samsung/odroid-xu3/setup.h
create mode 100644 configs/odroid-xu3_defconfig
create mode 100644 include/configs/odroid_xu3.h
--
1.8.3.2
^ permalink raw reply [flat|nested] 13+ messages in thread* [U-Boot] [PATCH v2 1/4] exynos5: fix GPIO information of exynos5420 2014-10-31 12:14 [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Hyungwon Hwang @ 2014-10-31 12:14 ` Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 Hyungwon Hwang ` (3 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Hyungwon Hwang @ 2014-10-31 12:14 UTC (permalink / raw) To: u-boot This patch fixes wrong GPIO information such as GPIO bank, table which is used to convert GPIO name to index, bank base address, and etc. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> --- arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- 2 files changed, 117 insertions(+), 126 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 7c5c4ff..da4ac6b 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -139,7 +139,7 @@ /* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 #define EXYNOS5420_PRO_ID 0x10000000 #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 @@ -161,11 +161,10 @@ #define EXYNOS5420_I2S_BASE 0x12D60000 #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 -#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 -#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 +#define EXYNOS5420_GPIO_PART1_BASE 0x13400000 +#define EXYNOS5420_GPIO_PART2_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART3_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART4_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000 diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 32e045a..431ae3a 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1028,83 +1028,7 @@ enum exynos5_gpio_pin { }; enum exynos5420_gpio_pin { - /* GPIO_PART1_STARTS */ - EXYNOS5420_GPIO_A00, /* 0 */ - EXYNOS5420_GPIO_A01, - EXYNOS5420_GPIO_A02, - EXYNOS5420_GPIO_A03, - EXYNOS5420_GPIO_A04, - EXYNOS5420_GPIO_A05, - EXYNOS5420_GPIO_A06, - EXYNOS5420_GPIO_A07, - EXYNOS5420_GPIO_A10, /* 8 */ - EXYNOS5420_GPIO_A11, - EXYNOS5420_GPIO_A12, - EXYNOS5420_GPIO_A13, - EXYNOS5420_GPIO_A14, - EXYNOS5420_GPIO_A15, - EXYNOS5420_GPIO_A16, - EXYNOS5420_GPIO_A17, - EXYNOS5420_GPIO_A20, /* 16 0x10 */ - EXYNOS5420_GPIO_A21, - EXYNOS5420_GPIO_A22, - EXYNOS5420_GPIO_A23, - EXYNOS5420_GPIO_A24, - EXYNOS5420_GPIO_A25, - EXYNOS5420_GPIO_A26, - EXYNOS5420_GPIO_A27, - EXYNOS5420_GPIO_B00, /* 24 0x18 */ - EXYNOS5420_GPIO_B01, - EXYNOS5420_GPIO_B02, - EXYNOS5420_GPIO_B03, - EXYNOS5420_GPIO_B04, - EXYNOS5420_GPIO_B05, - EXYNOS5420_GPIO_B06, - EXYNOS5420_GPIO_B07, - EXYNOS5420_GPIO_B10, /* 32 0x20 */ - EXYNOS5420_GPIO_B11, - EXYNOS5420_GPIO_B12, - EXYNOS5420_GPIO_B13, - EXYNOS5420_GPIO_B14, - EXYNOS5420_GPIO_B15, - EXYNOS5420_GPIO_B16, - EXYNOS5420_GPIO_B17, - EXYNOS5420_GPIO_B20, /* 40 0x28 */ - EXYNOS5420_GPIO_B21, - EXYNOS5420_GPIO_B22, - EXYNOS5420_GPIO_B23, - EXYNOS5420_GPIO_B24, - EXYNOS5420_GPIO_B25, - EXYNOS5420_GPIO_B26, - EXYNOS5420_GPIO_B27, - EXYNOS5420_GPIO_B30, /* 48 0x30 */ - EXYNOS5420_GPIO_B31, - EXYNOS5420_GPIO_B32, - EXYNOS5420_GPIO_B33, - EXYNOS5420_GPIO_B34, - EXYNOS5420_GPIO_B35, - EXYNOS5420_GPIO_B36, - EXYNOS5420_GPIO_B37, - EXYNOS5420_GPIO_B40, /* 56 0x38 */ - EXYNOS5420_GPIO_B41, - EXYNOS5420_GPIO_B42, - EXYNOS5420_GPIO_B43, - EXYNOS5420_GPIO_B44, - EXYNOS5420_GPIO_B45, - EXYNOS5420_GPIO_B46, - EXYNOS5420_GPIO_B47, - EXYNOS5420_GPIO_H00, /* 64 0x40 */ - EXYNOS5420_GPIO_H01, - EXYNOS5420_GPIO_H02, - EXYNOS5420_GPIO_H03, - EXYNOS5420_GPIO_H04, - EXYNOS5420_GPIO_H05, - EXYNOS5420_GPIO_H06, - EXYNOS5420_GPIO_H07, - - /* GPIO PART 2 STARTS*/ - EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */ - EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_Y70, EXYNOS5420_GPIO_Y71, EXYNOS5420_GPIO_Y72, EXYNOS5420_GPIO_Y73, @@ -1112,10 +1036,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y75, EXYNOS5420_GPIO_Y76, EXYNOS5420_GPIO_Y77, - - /* GPIO PART 3 STARTS*/ - EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */ - EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_X01, EXYNOS5420_GPIO_X02, EXYNOS5420_GPIO_X03, @@ -1123,7 +1044,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X05, EXYNOS5420_GPIO_X06, EXYNOS5420_GPIO_X07, - EXYNOS5420_GPIO_X10, /* 88 0x58 */ + EXYNOS5420_GPIO_X10, EXYNOS5420_GPIO_X11, EXYNOS5420_GPIO_X12, EXYNOS5420_GPIO_X13, @@ -1131,7 +1052,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X15, EXYNOS5420_GPIO_X16, EXYNOS5420_GPIO_X17, - EXYNOS5420_GPIO_X20, /* 96 0x60 */ + EXYNOS5420_GPIO_X20, EXYNOS5420_GPIO_X21, EXYNOS5420_GPIO_X22, EXYNOS5420_GPIO_X23, @@ -1139,7 +1060,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X25, EXYNOS5420_GPIO_X26, EXYNOS5420_GPIO_X27, - EXYNOS5420_GPIO_X30, /* 104 0x68 */ + EXYNOS5420_GPIO_X30, EXYNOS5420_GPIO_X31, EXYNOS5420_GPIO_X32, EXYNOS5420_GPIO_X33, @@ -1148,9 +1069,8 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X36, EXYNOS5420_GPIO_X37, - /* GPIO PART 4 STARTS*/ - EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */ - EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_1, EXYNOS5420_GPIO_C01, EXYNOS5420_GPIO_C02, EXYNOS5420_GPIO_C03, @@ -1158,7 +1078,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C05, EXYNOS5420_GPIO_C06, EXYNOS5420_GPIO_C07, - EXYNOS5420_GPIO_C10, /* 120 0x78 */ + EXYNOS5420_GPIO_C10, EXYNOS5420_GPIO_C11, EXYNOS5420_GPIO_C12, EXYNOS5420_GPIO_C13, @@ -1166,7 +1086,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C15, EXYNOS5420_GPIO_C16, EXYNOS5420_GPIO_C17, - EXYNOS5420_GPIO_C20, /* 128 0x80 */ + EXYNOS5420_GPIO_C20, EXYNOS5420_GPIO_C21, EXYNOS5420_GPIO_C22, EXYNOS5420_GPIO_C23, @@ -1174,7 +1094,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C25, EXYNOS5420_GPIO_C26, EXYNOS5420_GPIO_C27, - EXYNOS5420_GPIO_C30, /* 136 0x88 */ + EXYNOS5420_GPIO_C30, EXYNOS5420_GPIO_C31, EXYNOS5420_GPIO_C32, EXYNOS5420_GPIO_C33, @@ -1182,7 +1102,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C35, EXYNOS5420_GPIO_C36, EXYNOS5420_GPIO_C37, - EXYNOS5420_GPIO_C40, /* 144 0x90 */ + EXYNOS5420_GPIO_C40, EXYNOS5420_GPIO_C41, EXYNOS5420_GPIO_C42, EXYNOS5420_GPIO_C43, @@ -1190,7 +1110,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C45, EXYNOS5420_GPIO_C46, EXYNOS5420_GPIO_C47, - EXYNOS5420_GPIO_D10, /* 152 0x98 */ + EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_D11, EXYNOS5420_GPIO_D12, EXYNOS5420_GPIO_D13, @@ -1198,7 +1118,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_D15, EXYNOS5420_GPIO_D16, EXYNOS5420_GPIO_D17, - EXYNOS5420_GPIO_Y00, /* 160 0xa0 */ + EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_Y01, EXYNOS5420_GPIO_Y02, EXYNOS5420_GPIO_Y03, @@ -1206,7 +1126,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y05, EXYNOS5420_GPIO_Y06, EXYNOS5420_GPIO_Y07, - EXYNOS5420_GPIO_Y10, /* 168 0xa8 */ + EXYNOS5420_GPIO_Y10, EXYNOS5420_GPIO_Y11, EXYNOS5420_GPIO_Y12, EXYNOS5420_GPIO_Y13, @@ -1214,7 +1134,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y15, EXYNOS5420_GPIO_Y16, EXYNOS5420_GPIO_Y17, - EXYNOS5420_GPIO_Y20, /* 176 0xb0 */ + EXYNOS5420_GPIO_Y20, EXYNOS5420_GPIO_Y21, EXYNOS5420_GPIO_Y22, EXYNOS5420_GPIO_Y23, @@ -1222,7 +1142,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y25, EXYNOS5420_GPIO_Y26, EXYNOS5420_GPIO_Y27, - EXYNOS5420_GPIO_Y30, /* 184 0xb8 */ + EXYNOS5420_GPIO_Y30, EXYNOS5420_GPIO_Y31, EXYNOS5420_GPIO_Y32, EXYNOS5420_GPIO_Y33, @@ -1230,7 +1150,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y35, EXYNOS5420_GPIO_Y36, EXYNOS5420_GPIO_Y37, - EXYNOS5420_GPIO_Y40, /* 192 0xc0 */ + EXYNOS5420_GPIO_Y40, EXYNOS5420_GPIO_Y41, EXYNOS5420_GPIO_Y42, EXYNOS5420_GPIO_Y43, @@ -1238,7 +1158,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y45, EXYNOS5420_GPIO_Y46, EXYNOS5420_GPIO_Y47, - EXYNOS5420_GPIO_Y50, /* 200 0xc8 */ + EXYNOS5420_GPIO_Y50, EXYNOS5420_GPIO_Y51, EXYNOS5420_GPIO_Y52, EXYNOS5420_GPIO_Y53, @@ -1246,7 +1166,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y55, EXYNOS5420_GPIO_Y56, EXYNOS5420_GPIO_Y57, - EXYNOS5420_GPIO_Y60, /* 208 0xd0 */ + EXYNOS5420_GPIO_Y60, EXYNOS5420_GPIO_Y61, EXYNOS5420_GPIO_Y62, EXYNOS5420_GPIO_Y63, @@ -1255,9 +1175,8 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y66, EXYNOS5420_GPIO_Y67, - /* GPIO_PART5_STARTS */ - EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */ - EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, EXYNOS5420_GPIO_E01, EXYNOS5420_GPIO_E02, EXYNOS5420_GPIO_E03, @@ -1265,7 +1184,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_E05, EXYNOS5420_GPIO_E06, EXYNOS5420_GPIO_E07, - EXYNOS5420_GPIO_E10, /* 224 0xe0 */ + EXYNOS5420_GPIO_E10, EXYNOS5420_GPIO_E11, EXYNOS5420_GPIO_E12, EXYNOS5420_GPIO_E13, @@ -1273,7 +1192,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_E15, EXYNOS5420_GPIO_E16, EXYNOS5420_GPIO_E17, - EXYNOS5420_GPIO_F00, /* 232 0xe8 */ + EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_F01, EXYNOS5420_GPIO_F02, EXYNOS5420_GPIO_F03, @@ -1281,7 +1200,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_F05, EXYNOS5420_GPIO_F06, EXYNOS5420_GPIO_F07, - EXYNOS5420_GPIO_F10, /* 240 0xf0 */ + EXYNOS5420_GPIO_F10, EXYNOS5420_GPIO_F11, EXYNOS5420_GPIO_F12, EXYNOS5420_GPIO_F13, @@ -1289,7 +1208,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_F15, EXYNOS5420_GPIO_F16, EXYNOS5420_GPIO_F17, - EXYNOS5420_GPIO_G00, /* 248 0xf8 */ + EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_G01, EXYNOS5420_GPIO_G02, EXYNOS5420_GPIO_G03, @@ -1297,7 +1216,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G05, EXYNOS5420_GPIO_G06, EXYNOS5420_GPIO_G07, - EXYNOS5420_GPIO_G10, /* 256 0x100 */ + EXYNOS5420_GPIO_G10, EXYNOS5420_GPIO_G11, EXYNOS5420_GPIO_G12, EXYNOS5420_GPIO_G13, @@ -1305,7 +1224,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G15, EXYNOS5420_GPIO_G16, EXYNOS5420_GPIO_G17, - EXYNOS5420_GPIO_G20, /* 264 0x108 */ + EXYNOS5420_GPIO_G20, EXYNOS5420_GPIO_G21, EXYNOS5420_GPIO_G22, EXYNOS5420_GPIO_G23, @@ -1313,7 +1232,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G25, EXYNOS5420_GPIO_G26, EXYNOS5420_GPIO_G27, - EXYNOS5420_GPIO_J40, /* 272 0x110 */ + EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_J41, EXYNOS5420_GPIO_J42, EXYNOS5420_GPIO_J43, @@ -1322,15 +1241,89 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_J46, EXYNOS5420_GPIO_J47, - /* GPIO_PART6_STARTS */ - EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */ - EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5, + EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_A00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_A01, + EXYNOS5420_GPIO_A02, + EXYNOS5420_GPIO_A03, + EXYNOS5420_GPIO_A04, + EXYNOS5420_GPIO_A05, + EXYNOS5420_GPIO_A06, + EXYNOS5420_GPIO_A07, + EXYNOS5420_GPIO_A10, + EXYNOS5420_GPIO_A11, + EXYNOS5420_GPIO_A12, + EXYNOS5420_GPIO_A13, + EXYNOS5420_GPIO_A14, + EXYNOS5420_GPIO_A15, + EXYNOS5420_GPIO_A16, + EXYNOS5420_GPIO_A17, + EXYNOS5420_GPIO_A20, + EXYNOS5420_GPIO_A21, + EXYNOS5420_GPIO_A22, + EXYNOS5420_GPIO_A23, + EXYNOS5420_GPIO_A24, + EXYNOS5420_GPIO_A25, + EXYNOS5420_GPIO_A26, + EXYNOS5420_GPIO_A27, + EXYNOS5420_GPIO_B00, + EXYNOS5420_GPIO_B01, + EXYNOS5420_GPIO_B02, + EXYNOS5420_GPIO_B03, + EXYNOS5420_GPIO_B04, + EXYNOS5420_GPIO_B05, + EXYNOS5420_GPIO_B06, + EXYNOS5420_GPIO_B07, + EXYNOS5420_GPIO_B10, + EXYNOS5420_GPIO_B11, + EXYNOS5420_GPIO_B12, + EXYNOS5420_GPIO_B13, + EXYNOS5420_GPIO_B14, + EXYNOS5420_GPIO_B15, + EXYNOS5420_GPIO_B16, + EXYNOS5420_GPIO_B17, + EXYNOS5420_GPIO_B20, + EXYNOS5420_GPIO_B21, + EXYNOS5420_GPIO_B22, + EXYNOS5420_GPIO_B23, + EXYNOS5420_GPIO_B24, + EXYNOS5420_GPIO_B25, + EXYNOS5420_GPIO_B26, + EXYNOS5420_GPIO_B27, + EXYNOS5420_GPIO_B30, + EXYNOS5420_GPIO_B31, + EXYNOS5420_GPIO_B32, + EXYNOS5420_GPIO_B33, + EXYNOS5420_GPIO_B34, + EXYNOS5420_GPIO_B35, + EXYNOS5420_GPIO_B36, + EXYNOS5420_GPIO_B37, + EXYNOS5420_GPIO_B40, + EXYNOS5420_GPIO_B41, + EXYNOS5420_GPIO_B42, + EXYNOS5420_GPIO_B43, + EXYNOS5420_GPIO_B44, + EXYNOS5420_GPIO_B45, + EXYNOS5420_GPIO_B46, + EXYNOS5420_GPIO_B47, + EXYNOS5420_GPIO_H00, + EXYNOS5420_GPIO_H01, + EXYNOS5420_GPIO_H02, + EXYNOS5420_GPIO_H03, + EXYNOS5420_GPIO_H04, + EXYNOS5420_GPIO_H05, + EXYNOS5420_GPIO_H06, + EXYNOS5420_GPIO_H07, + + EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_4, EXYNOS5420_GPIO_Z1, EXYNOS5420_GPIO_Z2, EXYNOS5420_GPIO_Z3, EXYNOS5420_GPIO_Z4, EXYNOS5420_GPIO_Z5, EXYNOS5420_GPIO_Z6, + EXYNOS5420_GPIO_MAX_PORT }; @@ -1366,14 +1359,13 @@ static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, }; -#define EXYNOS5420_GPIO_NUM_PARTS 6 +#define EXYNOS5420_GPIO_NUM_PARTS 5 static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, - { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 }, - { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT }, + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, }; static inline struct gpio_info *get_gpio_data(void) @@ -1486,17 +1478,17 @@ static const struct gpio_name_num_table exynos5_gpio_table[] = { }; static const struct gpio_name_num_table exynos5420_gpio_table[] = { - GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), - GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), - GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), - GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0), GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), - GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0), + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0), GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0), { 0 } }; -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 2014-10-31 12:14 [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 1/4] exynos5: fix GPIO information of exynos5420 Hyungwon Hwang @ 2014-10-31 12:14 ` Hyungwon Hwang 2014-11-03 8:34 ` Lukasz Majewski 2014-10-31 12:14 ` [U-Boot] [PATCH v2 3/4] odroid: make some macros common Hyungwon Hwang ` (2 subsequent siblings) 4 siblings, 1 reply; 13+ messages in thread From: Hyungwon Hwang @ 2014-10-31 12:14 UTC (permalink / raw) To: u-boot The gpios of Exynos5800 are different from that of Exynos5420. This patch adds the gpio information and table of Exynos5800. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> --- arch/arm/include/asm/arch-exynos/gpio.h | 31 +++++++++++++++++++++++++++++-- drivers/gpio/s5p_gpio.c | 4 +++- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 431ae3a..8f82ef0 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1368,11 +1368,21 @@ static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, }; +#define EXYNOS5800_GPIO_NUM_PARTS 4 +static struct gpio_info exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = { + { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, + { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, + { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, + { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, +}; + static inline struct gpio_info *get_gpio_data(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_gpio_data; + else if (proid_is_exynos5800()) + return exynos5800_gpio_data; else return exynos5_gpio_data; } else if (cpu_is_exynos4()) { @@ -1388,8 +1398,10 @@ static inline struct gpio_info *get_gpio_data(void) static inline unsigned int get_bank_num(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return EXYNOS5420_GPIO_NUM_PARTS; + if (proid_is_exynos5800()) + return EXYNOS5800_GPIO_NUM_PARTS; else return EXYNOS5_GPIO_NUM_PARTS; } else if (cpu_is_exynos4()) { @@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = { { 0 } }; +static const struct gpio_name_num_table exynos5800_gpio_table[] = { + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0), + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0), + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0), + { 0 } +}; + void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index bcf44eb..bed7cd7 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char *name) */ #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) { + if (proid_is_exynos5420()) { tabp = exynos5420_gpio_table; irregular_bank_name = 'y'; irregular_set_number = '7'; irregular_bank_base = EXYNOS5420_GPIO_Y70; + } else if (proid_is_exynos5800()) { + tabp = exynos5800_gpio_table; } else { tabp = exynos5_gpio_table; irregular_bank_name = 'c'; -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 2014-10-31 12:14 ` [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 Hyungwon Hwang @ 2014-11-03 8:34 ` Lukasz Majewski 2014-11-04 1:26 ` Hyungwon Hwang 0 siblings, 1 reply; 13+ messages in thread From: Lukasz Majewski @ 2014-11-03 8:34 UTC (permalink / raw) To: u-boot Hi Hyungwon, > The gpios of Exynos5800 are different from that of Exynos5420. This > patch adds the gpio information and table of Exynos5800. > > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > --- > arch/arm/include/asm/arch-exynos/gpio.h | 31 > +++++++++++++++++++++++++++++-- > drivers/gpio/s5p_gpio.c | 4 +++- 2 files changed, 32 > insertions(+), 3 deletions(-) > > diff --git a/arch/arm/include/asm/arch-exynos/gpio.h > b/arch/arm/include/asm/arch-exynos/gpio.h index 431ae3a..8f82ef0 > 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h > +++ b/arch/arm/include/asm/arch-exynos/gpio.h > @@ -1368,11 +1368,21 @@ static struct gpio_info > exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = > { { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, }; > > +#define EXYNOS5800_GPIO_NUM_PARTS 4 > +static struct gpio_info > exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = { > + { EXYNOS5420_GPIO_PART1_BASE, > EXYNOS5420_GPIO_MAX_PORT_PART_1 }, > + { EXYNOS5420_GPIO_PART2_BASE, > EXYNOS5420_GPIO_MAX_PORT_PART_2 }, > + { EXYNOS5420_GPIO_PART3_BASE, > EXYNOS5420_GPIO_MAX_PORT_PART_3 }, > + { EXYNOS5420_GPIO_PART4_BASE, > EXYNOS5420_GPIO_MAX_PORT_PART_4 }, +}; > + > static inline struct gpio_info *get_gpio_data(void) > { > if (cpu_is_exynos5()) { > - if (proid_is_exynos5420() || proid_is_exynos5800()) > + if (proid_is_exynos5420()) > return exynos5420_gpio_data; > + else if (proid_is_exynos5800()) > + return exynos5800_gpio_data; > else > return exynos5_gpio_data; > } else if (cpu_is_exynos4()) { > @@ -1388,8 +1398,10 @@ static inline struct gpio_info > *get_gpio_data(void) static inline unsigned int get_bank_num(void) > { > if (cpu_is_exynos5()) { > - if (proid_is_exynos5420() || proid_is_exynos5800()) > + if (proid_is_exynos5420()) > return EXYNOS5420_GPIO_NUM_PARTS; > + if (proid_is_exynos5800()) > + return EXYNOS5800_GPIO_NUM_PARTS; I'm just wondering if Exynos5800 and Exynos5420 are not GPIO compatible? > else > return EXYNOS5_GPIO_NUM_PARTS; > } else if (cpu_is_exynos4()) { > @@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table > exynos5420_gpio_table[] = { { 0 } > }; > > +static const struct gpio_name_num_table exynos5800_gpio_table[] = { > + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), > + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), > + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0), > + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), > + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), > + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), > + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), > + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0), > + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), > + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), > + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0), > + { 0 } > +}; > + > void gpio_cfg_pin(int gpio, int cfg); > void gpio_set_pull(int gpio, int mode); > void gpio_set_drv(int gpio, int mode); > diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c > index bcf44eb..bed7cd7 100644 > --- a/drivers/gpio/s5p_gpio.c > +++ b/drivers/gpio/s5p_gpio.c > @@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char > *name) */ > #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) > if (cpu_is_exynos5()) { > - if (proid_is_exynos5420() || proid_is_exynos5800()) { > + if (proid_is_exynos5420()) { > tabp = exynos5420_gpio_table; > irregular_bank_name = 'y'; > irregular_set_number = '7'; > irregular_bank_base = EXYNOS5420_GPIO_Y70; > + } else if (proid_is_exynos5800()) { > + tabp = exynos5800_gpio_table; > } else { > tabp = exynos5_gpio_table; > irregular_bank_name = 'c'; -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 2014-11-03 8:34 ` Lukasz Majewski @ 2014-11-04 1:26 ` Hyungwon Hwang 0 siblings, 0 replies; 13+ messages in thread From: Hyungwon Hwang @ 2014-11-04 1:26 UTC (permalink / raw) To: u-boot Dear Lukasz, On Mon, 03 Nov 2014 09:34:12 +0100 Lukasz Majewski <l.majewski@samsung.com> wrote: > Hi Hyungwon, > > > The gpios of Exynos5800 are different from that of Exynos5420. This > > patch adds the gpio information and table of Exynos5800. > > > > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > > --- > > arch/arm/include/asm/arch-exynos/gpio.h | 31 > > +++++++++++++++++++++++++++++-- > > drivers/gpio/s5p_gpio.c | 4 +++- 2 files changed, 32 > > insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/include/asm/arch-exynos/gpio.h > > b/arch/arm/include/asm/arch-exynos/gpio.h index 431ae3a..8f82ef0 > > 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h > > +++ b/arch/arm/include/asm/arch-exynos/gpio.h > > @@ -1368,11 +1368,21 @@ static struct gpio_info > > exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = > > { { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, }; > > > > +#define EXYNOS5800_GPIO_NUM_PARTS 4 > > +static struct gpio_info > > exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = { > > + { EXYNOS5420_GPIO_PART1_BASE, > > EXYNOS5420_GPIO_MAX_PORT_PART_1 }, > > + { EXYNOS5420_GPIO_PART2_BASE, > > EXYNOS5420_GPIO_MAX_PORT_PART_2 }, > > + { EXYNOS5420_GPIO_PART3_BASE, > > EXYNOS5420_GPIO_MAX_PORT_PART_3 }, > > + { EXYNOS5420_GPIO_PART4_BASE, > > EXYNOS5420_GPIO_MAX_PORT_PART_4 }, +}; > > + > > static inline struct gpio_info *get_gpio_data(void) > > { > > if (cpu_is_exynos5()) { > > - if (proid_is_exynos5420() || proid_is_exynos5800()) > > + if (proid_is_exynos5420()) > > return exynos5420_gpio_data; > > + else if (proid_is_exynos5800()) > > + return exynos5800_gpio_data; > > else > > return exynos5_gpio_data; > > } else if (cpu_is_exynos4()) { > > @@ -1388,8 +1398,10 @@ static inline struct gpio_info > > *get_gpio_data(void) static inline unsigned int get_bank_num(void) > > { > > if (cpu_is_exynos5()) { > > - if (proid_is_exynos5420() || proid_is_exynos5800()) > > + if (proid_is_exynos5420()) > > return EXYNOS5420_GPIO_NUM_PARTS; > > + if (proid_is_exynos5800()) > > + return EXYNOS5800_GPIO_NUM_PARTS; > > I'm just wondering if Exynos5800 and Exynos5420 are not GPIO compatible? > Yes. You're right. I thought I miss the last page of GPIO specification of Exynos5800. This patch will be removed from Version 3. > > else > > return EXYNOS5_GPIO_NUM_PARTS; > > } else if (cpu_is_exynos4()) { > > @@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table > > exynos5420_gpio_table[] = { { 0 } > > }; > > > > +static const struct gpio_name_num_table exynos5800_gpio_table[] = { > > + GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), > > + GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), > > + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0), > > + GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), > > + GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), > > + GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), > > + GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), > > + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0), > > + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), > > + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), > > + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0), > > + { 0 } > > +}; > > + > > void gpio_cfg_pin(int gpio, int cfg); > > void gpio_set_pull(int gpio, int mode); > > void gpio_set_drv(int gpio, int mode); > > diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c > > index bcf44eb..bed7cd7 100644 > > --- a/drivers/gpio/s5p_gpio.c > > +++ b/drivers/gpio/s5p_gpio.c > > @@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char > > *name) */ > > #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) > > if (cpu_is_exynos5()) { > > - if (proid_is_exynos5420() || proid_is_exynos5800()) { > > + if (proid_is_exynos5420()) { > > tabp = exynos5420_gpio_table; > > irregular_bank_name = 'y'; > > irregular_set_number = '7'; > > irregular_bank_base = EXYNOS5420_GPIO_Y70; > > + } else if (proid_is_exynos5800()) { > > + tabp = exynos5800_gpio_table; > > } else { > > tabp = exynos5_gpio_table; > > irregular_bank_name = 'c'; > > > Best regards, Hyungwon Hwang -- Hyungwon Hwang S/W Platform Team, Software Center Samsung Electronics human.hwang at samsung.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/4] odroid: make some macros common 2014-10-31 12:14 [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 1/4] exynos5: fix GPIO information of exynos5420 Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 Hyungwon Hwang @ 2014-10-31 12:14 ` Hyungwon Hwang 2014-11-03 8:51 ` Lukasz Majewski 2014-10-31 12:14 ` [U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3 Hyungwon Hwang 2014-11-04 5:07 ` [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Jaehoon Chung 4 siblings, 1 reply; 13+ messages in thread From: Hyungwon Hwang @ 2014-10-31 12:14 UTC (permalink / raw) To: u-boot Some macros are used commonly for odroid series boards. This patch makes a common header file to congregate that kinds of macros. Even though there are more macros which can be common, they are not become common. Because they are a part of a register, the readability is better when they are defined at a place. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> --- board/samsung/odroid/odroid.c | 1 + board/samsung/odroid/setup.h | 8 -------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -18,6 +18,7 @@ #include <usb.h> #include <usb/s3c_udc.h> #include <samsung/misc.h> +#include "../setup.h" #include "setup.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 --- a/board/samsung/odroid/setup.h +++ b/board/samsung/odroid/setup.h @@ -8,14 +8,6 @@ #ifndef __ODROIDU3_SETUP__ #define __ODROIDU3_SETUP__ -/* A/M PLL_CON0 */ -#define SDIV(x) ((x) & 0x7) -#define PDIV(x) (((x) & 0x3f) << 8) -#define MDIV(x) (((x) & 0x3ff) << 16) -#define FSEL(x) (((x) & 0x1) << 27) -#define PLL_LOCKED_BIT (0x1 << 29) -#define PLL_ENABLE(x) (((x) & 0x1) << 31) - /* CLK_SRC_CPU */ #define MUX_APLL_SEL(x) ((x) & 0x1) #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/4] odroid: make some macros common 2014-10-31 12:14 ` [U-Boot] [PATCH v2 3/4] odroid: make some macros common Hyungwon Hwang @ 2014-11-03 8:51 ` Lukasz Majewski 2014-11-04 1:49 ` Hyungwon Hwang 0 siblings, 1 reply; 13+ messages in thread From: Lukasz Majewski @ 2014-11-03 8:51 UTC (permalink / raw) To: u-boot Hi Hyungwon, > Some macros are used commonly for odroid series boards. This patch > makes a common header file to congregate that kinds of macros. Even > though there are more macros which can be common, they are not become > common. Because they are a part of a register, the readability is > better when they are defined at a place. > > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > --- > board/samsung/odroid/odroid.c | 1 + > board/samsung/odroid/setup.h | 8 -------- > 2 files changed, 1 insertion(+), 8 deletions(-) > I suspect that you have not added the new file to git repository - since you only removed lines from board/samsung/odroid/setup.h I also guess that odroid U3 will not build anymore. That is a very good use case for buildman script. > diff --git a/board/samsung/odroid/odroid.c > b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 > --- a/board/samsung/odroid/odroid.c > +++ b/board/samsung/odroid/odroid.c > @@ -18,6 +18,7 @@ > #include <usb.h> > #include <usb/s3c_udc.h> > #include <samsung/misc.h> > +#include "../setup.h" Relative path is not a good idea IMHO. It would be better to place it at ./include/samsung/ with a self explanatory name (like exynos4-pll.h or/and exynos4-{other excluded defines for an IP blocks}). In this way other boards could use those defines too. > #include "setup.h" > > DECLARE_GLOBAL_DATA_PTR; > diff --git a/board/samsung/odroid/setup.h > b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 > --- a/board/samsung/odroid/setup.h > +++ b/board/samsung/odroid/setup.h > @@ -8,14 +8,6 @@ > #ifndef __ODROIDU3_SETUP__ > #define __ODROIDU3_SETUP__ > > -/* A/M PLL_CON0 */ > -#define SDIV(x) ((x) & 0x7) > -#define PDIV(x) (((x) & 0x3f) << 8) > -#define MDIV(x) (((x) & 0x3ff) << 16) > -#define FSEL(x) (((x) & 0x1) << 27) > -#define PLL_LOCKED_BIT (0x1 << 29) > -#define PLL_ENABLE(x) (((x) & 0x1) << 31) > - The above data is common for Exynos U3 and XU3, but is it the only one? Aren't there any more defines to be extracted? > /* CLK_SRC_CPU */ > #define MUX_APLL_SEL(x) ((x) & 0x1) > #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/4] odroid: make some macros common 2014-11-03 8:51 ` Lukasz Majewski @ 2014-11-04 1:49 ` Hyungwon Hwang 2014-11-04 8:29 ` Lukasz Majewski 0 siblings, 1 reply; 13+ messages in thread From: Hyungwon Hwang @ 2014-11-04 1:49 UTC (permalink / raw) To: u-boot On Mon, 03 Nov 2014 09:51:25 +0100 Lukasz Majewski <l.majewski@samsung.com> wrote: > Hi Hyungwon, > > > Some macros are used commonly for odroid series boards. This patch > > makes a common header file to congregate that kinds of macros. Even > > though there are more macros which can be common, they are not become > > common. Because they are a part of a register, the readability is > > better when they are defined at a place. > > > > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > > --- > > board/samsung/odroid/odroid.c | 1 + > > board/samsung/odroid/setup.h | 8 -------- > > 2 files changed, 1 insertion(+), 8 deletions(-) > > > > I suspect that you have not added the new file to git repository - since > you only removed lines from board/samsung/odroid/setup.h > > I also guess that odroid U3 will not build anymore. That is a very good > use case for buildman script. Oh. It is my mistake. I will include the common header in next version. > > > diff --git a/board/samsung/odroid/odroid.c > > b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 > > --- a/board/samsung/odroid/odroid.c > > +++ b/board/samsung/odroid/odroid.c > > @@ -18,6 +18,7 @@ > > #include <usb.h> > > #include <usb/s3c_udc.h> > > #include <samsung/misc.h> > > +#include "../setup.h" > > Relative path is not a good idea IMHO. > > It would be better to place it at ./include/samsung/ with a self > explanatory name (like exynos4-pll.h or/and exynos4-{other excluded > defines for an IP blocks}). > > In this way other boards could use those defines too. I think that your idea is better than mine. > > > #include "setup.h" > > > > DECLARE_GLOBAL_DATA_PTR; > > diff --git a/board/samsung/odroid/setup.h > > b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 > > --- a/board/samsung/odroid/setup.h > > +++ b/board/samsung/odroid/setup.h > > @@ -8,14 +8,6 @@ > > #ifndef __ODROIDU3_SETUP__ > > #define __ODROIDU3_SETUP__ > > > > -/* A/M PLL_CON0 */ > > -#define SDIV(x) ((x) & 0x7) > > -#define PDIV(x) (((x) & 0x3f) << 8) > > -#define MDIV(x) (((x) & 0x3ff) << 16) > > -#define FSEL(x) (((x) & 0x1) << 27) > > -#define PLL_LOCKED_BIT (0x1 << 29) > > -#define PLL_ENABLE(x) (((x) & 0x1) << 31) > > - > > The above data is common for Exynos U3 and XU3, but is it the only one? > Aren't there any more defines to be extracted? > > > /* CLK_SRC_CPU */ > > #define MUX_APLL_SEL(x) ((x) & 0x1) > > #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) > > > You're right. I found some other common macros more now. I will reflect it in next version. But I have a doubt about MUX_APLL_SEL or something else which consist of a register with different macros in different processors. They can be extracted to common file. But is it good to do it? For example, MUX_APLL_SEL exists both in Exynos4 and Exynos5's CLK_SRC_CPU. Exynos 4412 /* CLK_SRC_CPU */ #define MUX_APLL_SEL(x) ((x) & 0x1) #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) Exynos 5800 /* CLK_SRC_CPU */ #define MUX_APLL_SEL(x) ((x) & 0x1) #define MUX_CORE_SEL(x) (((x) & 0x1) #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) If MUX_APLL_SEL and MUX_CORE_SEL are extracted to the common file, it will be harder to see what consist of CLK_SRC_CPU at a glance. Isn't it? This situation is worse in the case of APLL_RATIO. (Please see the below.) I want to hear your opinion about it. Exynos 4412 /* CLK_DIV_CPU0 */ #define ARM_RATIO(x) ((x) & 0x7) #define CPUD_RATIO(x) (((x) & 0x7) << 4) #define ATB_RATIO(x) (((x) & 0x7) << 16) #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) #define APLL_RATIO(x) (((x) & 0x7) << 24) #define ARM2_RATIO(x) (((x) & 0x7) << 28) Exynos 5800 /* CLK_DIV_CPU0 */ #define CORE_RATIO(x) ((x) & 0x7) #define COREM0_RATIO(x) (((x) & 0x7) << 4) #define COREM1_RATIO(x) (((x) & 0x7) << 8) #define PERIPH_RATIO(x) (((x) & 0x7) << 12) #define ATB_RATIO(x) (((x) & 0x7) << 16) #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) #define APLL_RATIO(x) (((x) & 0x7) << 24) #define CORE2_RATIO(x) (((x) & 0x7) << 28) Thanks. Best regards, Hyungwon Hwang -- Hyungwon Hwang S/W Platform Team, Software Center Samsung Electronics human.hwang@samsung.com ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/4] odroid: make some macros common 2014-11-04 1:49 ` Hyungwon Hwang @ 2014-11-04 8:29 ` Lukasz Majewski 2014-11-04 10:56 ` Minkyu Kang 0 siblings, 1 reply; 13+ messages in thread From: Lukasz Majewski @ 2014-11-04 8:29 UTC (permalink / raw) To: u-boot Hi Hyungwon, > On Mon, 03 Nov 2014 09:51:25 +0100 > Lukasz Majewski <l.majewski@samsung.com> wrote: > > > Hi Hyungwon, > > > > > Some macros are used commonly for odroid series boards. This patch > > > makes a common header file to congregate that kinds of macros. > > > Even though there are more macros which can be common, they are > > > not become common. Because they are a part of a register, the > > > readability is better when they are defined at a place. > > > > > > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > > > --- > > > board/samsung/odroid/odroid.c | 1 + > > > board/samsung/odroid/setup.h | 8 -------- > > > 2 files changed, 1 insertion(+), 8 deletions(-) > > > > > > > I suspect that you have not added the new file to git repository - > > since you only removed lines from board/samsung/odroid/setup.h > > > > I also guess that odroid U3 will not build anymore. That is a very > > good use case for buildman script. > > Oh. It is my mistake. I will include the common header in next > version. > > > > > > diff --git a/board/samsung/odroid/odroid.c > > > b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 > > > --- a/board/samsung/odroid/odroid.c > > > +++ b/board/samsung/odroid/odroid.c > > > @@ -18,6 +18,7 @@ > > > #include <usb.h> > > > #include <usb/s3c_udc.h> > > > #include <samsung/misc.h> > > > +#include "../setup.h" > > > > Relative path is not a good idea IMHO. > > > > It would be better to place it at ./include/samsung/ with a self > > explanatory name (like exynos4-pll.h or/and exynos4-{other excluded > > defines for an IP blocks}). > > > > In this way other boards could use those defines too. > > I think that your idea is better than mine. > > > > > > #include "setup.h" > > > > > > DECLARE_GLOBAL_DATA_PTR; > > > diff --git a/board/samsung/odroid/setup.h > > > b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 > > > --- a/board/samsung/odroid/setup.h > > > +++ b/board/samsung/odroid/setup.h > > > @@ -8,14 +8,6 @@ > > > #ifndef __ODROIDU3_SETUP__ > > > #define __ODROIDU3_SETUP__ > > > > > > -/* A/M PLL_CON0 */ > > > -#define SDIV(x) ((x) & 0x7) > > > -#define PDIV(x) (((x) & 0x3f) << 8) > > > -#define MDIV(x) (((x) & 0x3ff) << 16) > > > -#define FSEL(x) (((x) & 0x1) << 27) > > > -#define PLL_LOCKED_BIT (0x1 << 29) > > > -#define PLL_ENABLE(x) (((x) & 0x1) << 31) > > > - > > > > The above data is common for Exynos U3 and XU3, but is it the only > > one? Aren't there any more defines to be extracted? > > > > > /* CLK_SRC_CPU */ > > > #define MUX_APLL_SEL(x) ((x) & 0x1) > > > #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) > > > > > > > > You're right. I found some other common macros more now. I will > reflect it in next version. But I have a doubt about MUX_APLL_SEL or > something else which consist of a register with different macros in > different processors. They can be extracted to common file. But is it > good to do it? For example, MUX_APLL_SEL exists both in Exynos4 and > Exynos5's CLK_SRC_CPU. > > Exynos 4412 > /* CLK_SRC_CPU */ > #define MUX_APLL_SEL(x) ((x) & 0x1) > #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) > > Exynos 5800 > /* CLK_SRC_CPU */ > #define MUX_APLL_SEL(x) ((x) & 0x1) > #define MUX_CORE_SEL(x) (((x) & 0x1) > #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) > #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) It is always a matter of pragmatism. In the above case you could only extract MUX_APLL_SEL(x). But is it worth to add a separate header file for only one line? In my opinion not. > > If MUX_APLL_SEL and MUX_CORE_SEL are extracted to the common file, it > will be harder to see what consist of CLK_SRC_CPU at a glance. Isn't > it? This situation is worse in the case of APLL_RATIO. (Please see > the below.) I want to hear your opinion about it. > > Exynos 4412 > /* CLK_DIV_CPU0 */ > #define ARM_RATIO(x) ((x) & 0x7) > #define CPUD_RATIO(x) (((x) & 0x7) << 4) > #define ATB_RATIO(x) (((x) & 0x7) << 16) > #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) > #define APLL_RATIO(x) (((x) & 0x7) << 24) > #define ARM2_RATIO(x) (((x) & 0x7) << 28) > > Exynos 5800 > /* CLK_DIV_CPU0 */ > #define CORE_RATIO(x) ((x) & 0x7) > #define COREM0_RATIO(x) (((x) & 0x7) << 4) > #define COREM1_RATIO(x) (((x) & 0x7) << 8) > #define PERIPH_RATIO(x) (((x) & 0x7) << 12) > #define ATB_RATIO(x) (((x) & 0x7) << 16) > #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) > #define APLL_RATIO(x) (((x) & 0x7) << 24) > #define CORE2_RATIO(x) (((x) & 0x7) << 28) Readability is important. Also please pay a note that ARM2_RATIO() is the same as CORE2_RATIO(). Frankly I don't know why those defines have different names. To sum up: When you see a potential to extract a common data and it justifies the need for creating a new file, then go for it. Is the setup.h the best candidate for data extraction? Hard to say. If there aren't many defines to be easily extracted, then we can leave things as they are with separate setup.h for XU3. > > Thanks. > > Best regards, > Hyungwon Hwang > -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 3/4] odroid: make some macros common 2014-11-04 8:29 ` Lukasz Majewski @ 2014-11-04 10:56 ` Minkyu Kang 0 siblings, 0 replies; 13+ messages in thread From: Minkyu Kang @ 2014-11-04 10:56 UTC (permalink / raw) To: u-boot Dear Hyungwon Hwang, On 04/11/14 17:29, Lukasz Majewski wrote: > Hi Hyungwon, > >> On Mon, 03 Nov 2014 09:51:25 +0100 >> Lukasz Majewski <l.majewski@samsung.com> wrote: >> >>> Hi Hyungwon, >>> >>>> Some macros are used commonly for odroid series boards. This patch >>>> makes a common header file to congregate that kinds of macros. >>>> Even though there are more macros which can be common, they are >>>> not become common. Because they are a part of a register, the >>>> readability is better when they are defined at a place. >>>> >>>> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> >>>> --- >>>> board/samsung/odroid/odroid.c | 1 + >>>> board/samsung/odroid/setup.h | 8 -------- >>>> 2 files changed, 1 insertion(+), 8 deletions(-) >>>> >>> >>> I suspect that you have not added the new file to git repository - >>> since you only removed lines from board/samsung/odroid/setup.h >>> >>> I also guess that odroid U3 will not build anymore. That is a very >>> good use case for buildman script. >> >> Oh. It is my mistake. I will include the common header in next >> version. >> >>> >>>> diff --git a/board/samsung/odroid/odroid.c >>>> b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 >>>> --- a/board/samsung/odroid/odroid.c >>>> +++ b/board/samsung/odroid/odroid.c >>>> @@ -18,6 +18,7 @@ >>>> #include <usb.h> >>>> #include <usb/s3c_udc.h> >>>> #include <samsung/misc.h> >>>> +#include "../setup.h" >>> >>> Relative path is not a good idea IMHO. >>> >>> It would be better to place it at ./include/samsung/ with a self >>> explanatory name (like exynos4-pll.h or/and exynos4-{other excluded >>> defines for an IP blocks}). >>> >>> In this way other boards could use those defines too. >> >> I think that your idea is better than mine. >> >>> >>>> #include "setup.h" >>>> >>>> DECLARE_GLOBAL_DATA_PTR; >>>> diff --git a/board/samsung/odroid/setup.h >>>> b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 >>>> --- a/board/samsung/odroid/setup.h >>>> +++ b/board/samsung/odroid/setup.h >>>> @@ -8,14 +8,6 @@ >>>> #ifndef __ODROIDU3_SETUP__ >>>> #define __ODROIDU3_SETUP__ >>>> >>>> -/* A/M PLL_CON0 */ >>>> -#define SDIV(x) ((x) & 0x7) >>>> -#define PDIV(x) (((x) & 0x3f) << 8) >>>> -#define MDIV(x) (((x) & 0x3ff) << 16) >>>> -#define FSEL(x) (((x) & 0x1) << 27) >>>> -#define PLL_LOCKED_BIT (0x1 << 29) >>>> -#define PLL_ENABLE(x) (((x) & 0x1) << 31) >>>> - >>> >>> The above data is common for Exynos U3 and XU3, but is it the only >>> one? Aren't there any more defines to be extracted? >>> >>>> /* CLK_SRC_CPU */ >>>> #define MUX_APLL_SEL(x) ((x) & 0x1) >>>> #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) >>> >>> >>> >> >> You're right. I found some other common macros more now. I will >> reflect it in next version. But I have a doubt about MUX_APLL_SEL or >> something else which consist of a register with different macros in >> different processors. They can be extracted to common file. But is it >> good to do it? For example, MUX_APLL_SEL exists both in Exynos4 and >> Exynos5's CLK_SRC_CPU. >> >> Exynos 4412 >> /* CLK_SRC_CPU */ >> #define MUX_APLL_SEL(x) ((x) & 0x1) >> #define MUX_CORE_SEL(x) (((x) & 0x1) << 16) >> >> Exynos 5800 >> /* CLK_SRC_CPU */ >> #define MUX_APLL_SEL(x) ((x) & 0x1) >> #define MUX_CORE_SEL(x) (((x) & 0x1) >> #define MUX_HPM_SEL(x) (((x) & 0x1) << 20) >> #define MUX_MPLL_USER_SEL_C(x) (((x) & 0x1) << 24) > > It is always a matter of pragmatism. In the above case you could only > extract MUX_APLL_SEL(x). But is it worth to add a separate header file > for only one line? In my opinion not. > >> >> If MUX_APLL_SEL and MUX_CORE_SEL are extracted to the common file, it >> will be harder to see what consist of CLK_SRC_CPU at a glance. Isn't >> it? This situation is worse in the case of APLL_RATIO. (Please see >> the below.) I want to hear your opinion about it. >> >> Exynos 4412 >> /* CLK_DIV_CPU0 */ >> #define ARM_RATIO(x) ((x) & 0x7) >> #define CPUD_RATIO(x) (((x) & 0x7) << 4) >> #define ATB_RATIO(x) (((x) & 0x7) << 16) >> #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) >> #define APLL_RATIO(x) (((x) & 0x7) << 24) >> #define ARM2_RATIO(x) (((x) & 0x7) << 28) >> >> Exynos 5800 >> /* CLK_DIV_CPU0 */ >> #define CORE_RATIO(x) ((x) & 0x7) >> #define COREM0_RATIO(x) (((x) & 0x7) << 4) >> #define COREM1_RATIO(x) (((x) & 0x7) << 8) >> #define PERIPH_RATIO(x) (((x) & 0x7) << 12) >> #define ATB_RATIO(x) (((x) & 0x7) << 16) >> #define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) >> #define APLL_RATIO(x) (((x) & 0x7) << 24) >> #define CORE2_RATIO(x) (((x) & 0x7) << 28) > > Readability is important. Also please pay a note that ARM2_RATIO() is > the same as CORE2_RATIO(). Frankly I don't know why those defines have > different names. > > To sum up: > > When you see a potential to extract a common data and it justifies the > need for creating a new file, then go for it. > > Is the setup.h the best candidate for data extraction? Hard to say. > > If there aren't many defines to be easily extracted, then we can leave > things as they are with separate setup.h for XU3. > Actually, such a clock setting is expected to done at IPL or sboot. So I did not consider detailed clock controls. For now, I concluded such settings are board specific feature. So I think, new setup file is better. Thanks, Minkyu Kang. ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3 2014-10-31 12:14 [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Hyungwon Hwang ` (2 preceding siblings ...) 2014-10-31 12:14 ` [U-Boot] [PATCH v2 3/4] odroid: make some macros common Hyungwon Hwang @ 2014-10-31 12:14 ` Hyungwon Hwang 2014-11-03 9:09 ` Lukasz Majewski 2014-11-04 5:07 ` [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Jaehoon Chung 4 siblings, 1 reply; 13+ messages in thread From: Hyungwon Hwang @ 2014-10-31 12:14 UTC (permalink / raw) To: u-boot This patch adds support for Odroid-XU3. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> --- arch/arm/cpu/armv7/exynos/Kconfig | 4 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 72 +++++++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 ++++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 132 ++++++++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 115 +++++++++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 ++ include/configs/odroid_xu3.h | 73 +++++++++++++++++++ 10 files changed, 427 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 3a25fee..a47cb34 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -22,6 +22,9 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board" +config TARGET_ODROID_XU3 + bool "Exynos5422 Odroid board" + config TARGET_ARNDALE bool "Exynos5250 Arndale board" select OF_CONTROL if !SPL_BUILD @@ -60,6 +63,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2dcfcc0..66191f9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ - exynos5800-peach-pi.dtb + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..34f52c6 --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,72 @@ +/* + * Odroid XU3 device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos54xx.dtsi" + +/ { + model = "Odroid XU3 based on EXYNOS5422"; + compatible = "samsung,odroidxu3", "samsung,exynos5"; + + config { + hwid = "smdk5420 TEST A-A 9382"; + }; + + aliases { + serial0 = "/serial at 12C00000"; + console = "/serial at 12C20000"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000 + 0x80000000 0x10000000 + 0x90000000 0x10000000 + 0xa0000000 0x10000000 + 0xb0000000 0xea00000>; + }; + + serial at 12C20000 { + status="okay"; + }; + + /* s2mps11 is on i2c bus 4 */ + i2c at 12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + pmic at 66 { + reg = <0x66>; + compatible = "samsung,s2mps11-pmic"; + }; + }; + + mmc at 12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc at 12210000 { + status = "disabled"; + }; + + mmc at 12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc at 12230000 { + status = "disabled"; + }; +}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "odroid-xu3" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang <human.hwang@samsung.com> +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..f1d8667 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Hyungwon Hwang <human.hwang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/power.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sromc.h> +#include "../setup.h" +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int get_board_rev(void) +{ + unsigned int rev = 0; + return rev; +} + +int exynos_init(void) +{ + return 0; +} + +static int board_clock_init(void) +{ + unsigned int set, clr, clr_src_cpu, clr_pll_con0; + struct exynos5420_clock *clk = (struct exynos5420_clock *) + samsung_get_base_clock(); + /* + * CMU_CPU clocks src to MPLL + * Bit values: 0 ; 1 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL + */ + + /* Set CMU_CPU clocks src to OSCCLK */ + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1); + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1); + + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + /* Set APLL to 1200MHz */ + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | + PLL_ENABLE(1); + set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); + + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CMU_CPU clocks src to APLL */ + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0); + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) | + PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7); + set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) | + PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0); + + clrsetbits_le32(&clk->div_cpu0, clr, set); + + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) + continue; + + /* Set MPLL to 800MHz */ + set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); + + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CLKMUX_UART src to MPLL */ + clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7); + set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3); + + clrsetbits_le32(&clk->src_peric0, clr, set); + + /* Set SCLK_UART to 400 MHz (MPLL / 2) */ + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | + UART3_RATIO(15); + set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) | + UART3_RATIO(1); + + clrsetbits_le32(&clk->div_peric0, clr, set); + + while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING) + continue; + + /* Set CLKMUX_MMC src to MPLL */ + clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7); + set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3); + + clrsetbits_le32(&clk->src_fsys, clr, set); + + clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff); + set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0); + + clrsetbits_le32(&clk->div_fsys1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) + continue; + + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int exynos_early_init_f(void) +{ + return board_clock_init(); +} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..afec01f --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2014 Samsung Electronics + * Hyungwon Hwang <human.hwang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__ + +/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) + +/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \ + (x) & APLL_SEL(1) || \ + (x) & CORE_SEL(0) || \ + (x) & CORE_SEL(1)) + +/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28) + +/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28) + +#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \ + DIV_ATB(DIV_STAT_CHANGING) | \ + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ + DIV_APLL(DIV_STAT_CHANGING) | \ + DIV_ARM2(DIV_STAT_CHANGING)) + +/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16) + +/* Set CLK_DIV_PERIL0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20) + +/* Set CLK_DIV_STAT_PERIL0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16) + +#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ + DIV_UART3(DIV_STAT_CHANGING) | \ + DIV_UART2(DIV_STAT_CHANGING) | \ + DIV_UART1(DIV_STAT_CHANGING) | \ + DIV_UART0(DIV_STAT_CHANGING)) + +/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16) + +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20) + +#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28) + +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ + DIV_MMC1(DIV_STAT_CHANGING) | \ + DIV_MMC2(DIV_STAT_CHANGING)) + +#define MPLL_FOUT_SEL_SHIFT 4 +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ +#define TIMEOUT_EPLL_LOCK 1000 + +#define AUDIO_0_RATIO_MASK 0x0f +#define AUDIO_1_RATIO_MASK 0x0f + +#define AUDIO0_SEL_MASK 0xf +#define AUDIO1_SEL_MASK 0xf + +#define CLK_SRC_SCLK_EPLL 0x7 +#define CLK_SRC_MOUT_EPLL (1<<12) +#define AUDIO_CLKMUX_ASS (1<<0) + +/* CON0 bit-fields */ +#define EPLL_CON0_MDIV_MASK 0x1ff +#define EPLL_CON0_PDIV_MASK 0x3f +#define EPLL_CON0_SDIV_MASK 0x7 +#define EPLL_CON0_MDIV_SHIFT 16 +#define EPLL_CON0_PDIV_SHIFT 8 +#define EPLL_CON0_SDIV_SHIFT 0 +#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 +#define EPLL_CON0_LOCK_DET_EN_MASK 1 + +#define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 +#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..867ac74 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang <human.hwang@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include "exynos5-common.h" + +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3" + +#define CONFIG_OF_CONTROL +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */ + +#define TZPC_BASE_OFFSET 0x10000 + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT + +/* + * FIXME: The number of bank is actually 8. But there is no way to reserver the + * last 16 Mib in the last bank now. So I just excluded the last bank + * temporally. + */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_ENV_IS_IN_MMC + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT + +#undef CONFIG_EXYNOS_SPL +#undef CONFIG_SILENT_CONSOLE +#undef CONFIG_CROS_EC +#undef CONFIG_CROS_EC_SPI +#undef CONFIG_CROS_EC_I2C +#undef CONFIG_CROS_EC_KEYB +#undef CONFIG_CMD_CROS_EC +#undef CONFIG_KEYBOARD +#undef CONFIG_SPI_BOOTING +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_SPI_FLASH +#undef CONFIG_EXYNOS_SPI +#undef CONFIG_CMD_SF +#undef CONFIG_CMD_SPI +#undef CONFIG_SPI_FLASH_WINBOND +#undef CONFIG_SPI_FLASH_GIGADEVICE +#undef CONFIG_OF_SPI +#undef CONFIG_FIT_BEST_MATCH +#undef CONFIG_USB_BOOTING +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#undef CONFIG_ENV_IS_IN_SPI_FLASH + + +#endif /* __CONFIG_H */ -- 1.8.3.2 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3 2014-10-31 12:14 ` [U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3 Hyungwon Hwang @ 2014-11-03 9:09 ` Lukasz Majewski 0 siblings, 0 replies; 13+ messages in thread From: Lukasz Majewski @ 2014-11-03 9:09 UTC (permalink / raw) To: u-boot Hi Hyungwon, > This patch adds support for Odroid-XU3. > > Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> > --- > arch/arm/cpu/armv7/exynos/Kconfig | 4 ++ > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/exynos5422-odroidxu3.dts | 72 +++++++++++++++++++ > board/samsung/odroid-xu3/Kconfig | 12 ++++ > board/samsung/odroid-xu3/MAINTAINERS | 6 ++ > board/samsung/odroid-xu3/Makefile | 7 ++ > board/samsung/odroid-xu3/odroid-xu3.c | 132 > ++++++++++++++++++++++++++++++++++ > board/samsung/odroid-xu3/setup.h | 115 > +++++++++++++++++++++++++++++ configs/odroid-xu3_defconfig > | 4 ++ include/configs/odroid_xu3.h | 73 > +++++++++++++++++++ 10 files changed, 427 insertions(+), 1 > deletion(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts > create mode 100644 board/samsung/odroid-xu3/Kconfig create mode > 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 > board/samsung/odroid-xu3/Makefile create mode 100644 > board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 > board/samsung/odroid-xu3/setup.h create mode 100644 > configs/odroid-xu3_defconfig create mode 100644 > include/configs/odroid_xu3.h > > diff --git a/arch/arm/cpu/armv7/exynos/Kconfig > b/arch/arm/cpu/armv7/exynos/Kconfig index 3a25fee..a47cb34 100644 > --- a/arch/arm/cpu/armv7/exynos/Kconfig > +++ b/arch/arm/cpu/armv7/exynos/Kconfig > @@ -22,6 +22,9 @@ config TARGET_TRATS2 > config TARGET_ODROID > bool "Exynos4412 Odroid board" > > +config TARGET_ODROID_XU3 > + bool "Exynos5422 Odroid board" > + > config TARGET_ARNDALE > bool "Exynos5250 Arndale board" > select OF_CONTROL if !SPL_BUILD > @@ -60,6 +63,7 @@ source "board/samsung/universal_c210/Kconfig" > source "board/samsung/origen/Kconfig" > source "board/samsung/trats2/Kconfig" > source "board/samsung/odroid/Kconfig" > +source "board/samsung/odroid-xu3/Kconfig" > source "board/samsung/arndale/Kconfig" > source "board/samsung/smdk5250/Kconfig" > source "board/samsung/smdk5420/Kconfig" > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 2dcfcc0..66191f9 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ > exynos5250-smdk5250.dtb \ > exynos5420-smdk5420.dtb \ > exynos5420-peach-pit.dtb \ > - exynos5800-peach-pi.dtb > + exynos5800-peach-pi.dtb \ > + exynos5422-odroidxu3.dtb > dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ > tegra20-medcom-wide.dtb \ > tegra20-paz00.dtb \ > diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts > b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 > index 0000000..34f52c6 > --- /dev/null > +++ b/arch/arm/dts/exynos5422-odroidxu3.dts > @@ -0,0 +1,72 @@ > +/* > + * Odroid XU3 device tree source > + * > + * Copyright (c) 2014 Samsung Electronics Co., Ltd. > + * http://www.samsung.com > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +/dts-v1/; > +/include/ "exynos54xx.dtsi" > + > +/ { > + model = "Odroid XU3 based on EXYNOS5422"; > + compatible = "samsung,odroidxu3", "samsung,exynos5"; > + > + config { > + hwid = "smdk5420 TEST A-A 9382"; > + }; > + > + aliases { > + serial0 = "/serial at 12C00000"; > + console = "/serial at 12C20000"; > + }; > + > + memory { > + device_type = "memory"; > + reg = <0x40000000 0x10000000 > + 0x50000000 0x10000000 > + 0x60000000 0x10000000 > + 0x70000000 0x10000000 > + 0x80000000 0x10000000 > + 0x90000000 0x10000000 > + 0xa0000000 0x10000000 > + 0xb0000000 0xea00000>; > + }; > + > + serial at 12C20000 { > + status="okay"; > + }; > + > + /* s2mps11 is on i2c bus 4 */ > + i2c at 12ca0000 { > + #address-cells = <1>; > + #size-cells = <0>; > + pmic at 66 { > + reg = <0x66>; > + compatible = "samsung,s2mps11-pmic"; > + }; > + }; > + > + mmc at 12200000 { > + samsung,bus-width = <8>; > + samsung,timing = <1 3 3>; > + samsung,removable = <0>; > + samsung,pre-init; > + }; > + > + mmc at 12210000 { > + status = "disabled"; > + }; > + > + mmc at 12220000 { > + samsung,bus-width = <4>; > + samsung,timing = <1 2 3>; > + samsung,removable = <1>; > + }; > + > + mmc at 12230000 { > + status = "disabled"; > + }; > +}; > diff --git a/board/samsung/odroid-xu3/Kconfig > b/board/samsung/odroid-xu3/Kconfig new file mode 100644 > index 0000000..6159692 > --- /dev/null > +++ b/board/samsung/odroid-xu3/Kconfig > @@ -0,0 +1,12 @@ > +if TARGET_ODROID_XU3 > + > +config SYS_BOARD > + default "odroid-xu3" > + > +config SYS_VENDOR > + default "samsung" > + > +config SYS_CONFIG_NAME > + default "odroid_xu3" > + > +endif > diff --git a/board/samsung/odroid-xu3/MAINTAINERS > b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 > index 0000000..50cf928 > --- /dev/null > +++ b/board/samsung/odroid-xu3/MAINTAINERS > @@ -0,0 +1,6 @@ > +ODROID-XU3 BOARD > +M: Hyungwon Hwang <human.hwang@samsung.com> > +S: Maintained > +F: board/samsung/odroid-xu3/ > +F: include/configs/odroid_xu3.h > +F: configs/odroid-xu3_defconfig > diff --git a/board/samsung/odroid-xu3/Makefile > b/board/samsung/odroid-xu3/Makefile new file mode 100644 > index 0000000..85ae5c5 > --- /dev/null > +++ b/board/samsung/odroid-xu3/Makefile > @@ -0,0 +1,7 @@ > +# > +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights > reserved. +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +obj-y := odroid-xu3.o > diff --git a/board/samsung/odroid-xu3/odroid-xu3.c > b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 > index 0000000..f1d8667 > --- /dev/null > +++ b/board/samsung/odroid-xu3/odroid-xu3.c > @@ -0,0 +1,132 @@ > +/* > + * Copyright (C) 2014 Samsung Electronics > + * Hyungwon Hwang <human.hwang@samsung.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <netdev.h> > +#include <asm/arch/cpu.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/power.h> > +#include <asm/arch/gpio.h> > +#include <asm/arch/mmc.h> > +#include <asm/arch/pinmux.h> > +#include <asm/arch/sromc.h> > +#include "../setup.h" > +#include "setup.h" I've pointed it out in the previous mail. > + > +DECLARE_GLOBAL_DATA_PTR; > + > +unsigned int get_board_rev(void) > +{ > + unsigned int rev = 0; > + return rev; > +} > + > +int exynos_init(void) > +{ > + return 0; > +} > + > +static int board_clock_init(void) > +{ > + unsigned int set, clr, clr_src_cpu, clr_pll_con0; > + struct exynos5420_clock *clk = (struct exynos5420_clock *) > + > samsung_get_base_clock(); > + /* > + * CMU_CPU clocks src to MPLL > + * Bit values: 0 ; 1 > + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL > + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL > + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C > + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL > + */ > + > + /* Set CMU_CPU clocks src to OSCCLK */ > + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1); > + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1); > + > + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); > + > + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) > + continue; > + > + /* Set APLL to 1200MHz */ > + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | > + PLL_ENABLE(1); > + set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1); > + > + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); > + > + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) > + continue; > + > + /* Set CMU_CPU clocks src to APLL */ > + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0); > + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); > + > + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) > + continue; > + > + clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) | > + PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7); > + set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) | > + PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0); > + > + clrsetbits_le32(&clk->div_cpu0, clr, set); > + > + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) > + continue; > + > + /* Set MPLL to 800MHz */ > + set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1); > + > + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); > + > + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) > + continue; > + > + /* Set CLKMUX_UART src to MPLL */ > + clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | > UART3_SEL(7); > + set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | > UART3_SEL(3); + > + clrsetbits_le32(&clk->src_peric0, clr, set); > + > + /* Set SCLK_UART to 400 MHz (MPLL / 2) */ > + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | > + UART3_RATIO(15); > + set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) | > + UART3_RATIO(1); > + > + clrsetbits_le32(&clk->div_peric0, clr, set); > + > + while (readl(&clk->div_stat_peric0) & > DIV_STAT_PERIC0_CHANGING) > + continue; > + > + /* Set CLKMUX_MMC src to MPLL */ > + clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7); > + set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3); > + > + clrsetbits_le32(&clk->src_fsys, clr, set); > + > + clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | > MMC2_RATIO(0x3ff); > + set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0); > + > + clrsetbits_le32(&clk->div_fsys1, clr, set); > + > + /* Wait for divider ready status */ > + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) > + continue; > + > + return 0; > +} > + > +#ifdef CONFIG_BOARD_EARLY_INIT_F > +int exynos_early_init_f(void) > +{ > + return board_clock_init(); > +} > +#endif > diff --git a/board/samsung/odroid-xu3/setup.h > b/board/samsung/odroid-xu3/setup.h new file mode 100644 > index 0000000..afec01f > --- /dev/null > +++ b/board/samsung/odroid-xu3/setup.h > @@ -0,0 +1,115 @@ > +/* > + * (C) Copyright 2014 Samsung Electronics > + * Hyungwon Hwang <human.hwang@samsung.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __ODROID_XU3_SETUP__ > +#define __ODROID_XU3_SETUP__ > + > +/* CLK_SRC_CPU */ > +#define MUX_APLL_SEL(x) ((x) & 0x1) > +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) > + > +/* CLK_MUX_STAT_CPU */ > +#define APLL_SEL(x) ((x) & 0x7) > +#define CORE_SEL(x) (((x) & 0x7) << 16) > +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) > || \ > + (x) & APLL_SEL(1) > || \ > + (x) & CORE_SEL(0) > || \ > + (x) & CORE_SEL(1)) > + > +/* CLK_DIV_CPU0 */ > +#define ARM_RATIO(x) ((x) & 0x7) > +#define CPUD_RATIO(x) (((x) & 0x7) << 4) > +#define ATB_RATIO(x) (((x) & 0x7) << 16) > +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) > +#define APLL_RATIO(x) (((x) & 0x7) << 24) > +#define ARM2_RATIO(x) (((x) & 0x7) << 28) > + > +/* CLK_DIV_STAT_CPU0 */ > +#define DIV_CPUD(x) (((x) & 0x1) << 4) > +#define DIV_ATB(x) (((x) & 0x1) << 16) > +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) > +#define DIV_APLL(x) (((x) & 0x1) << 24) > +#define DIV_ARM2(x) (((x) & 0x1) << 28) > + > +#define DIV_STAT_CHANGING 0x1 > +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \ > + DIV_ATB(DIV_STAT_CHANGING) | \ > + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ > + DIV_APLL(DIV_STAT_CHANGING) | \ > + DIV_ARM2(DIV_STAT_CHANGING)) > + > +/* Set CLK_SRC_PERIC0 */ > +#define UART0_SEL(x) (((x) & 0xf) << 4) > +#define UART1_SEL(x) (((x) & 0xf) << 8) > +#define UART2_SEL(x) (((x) & 0xf) << 12) > +#define UART3_SEL(x) (((x) & 0xf) << 16) > + > +/* Set CLK_DIV_PERIL0 */ > +#define UART0_RATIO(x) (((x) & 0xf) << 8) > +#define UART1_RATIO(x) (((x) & 0xf) << 12) > +#define UART2_RATIO(x) (((x) & 0xf) << 16) > +#define UART3_RATIO(x) (((x) & 0xf) << 20) > + > +/* Set CLK_DIV_STAT_PERIL0 */ > +#define DIV_UART0(x) ((x) & 0x1) > +#define DIV_UART1(x) (((x) & 0x1) << 4) > +#define DIV_UART2(x) (((x) & 0x1) << 8) > +#define DIV_UART3(x) (((x) & 0x1) << 12) > +#define DIV_UART4(x) (((x) & 0x1) << 16) > + > +#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ > + DIV_UART3(DIV_STAT_CHANGING) | \ > + DIV_UART2(DIV_STAT_CHANGING) | \ > + DIV_UART1(DIV_STAT_CHANGING) | \ > + DIV_UART0(DIV_STAT_CHANGING)) > + > +/* CLK_SRC_FSYS */ > +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) > +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) > +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16) > + > +/* CLK_DIV_FSYS1 */ > +#define MMC0_RATIO(x) ((x) & 0x3ff) > +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) > +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20) > + > +#define DIV_MMC0(x) (((x) & 1) << 20) > +#define DIV_MMC1(x) (((x) & 1) << 24) > +#define DIV_MMC2(x) (((x) & 1) << 28) > + > +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) > | \ > + DIV_MMC1(DIV_STAT_CHANGING) | \ > + DIV_MMC2(DIV_STAT_CHANGING)) > + > +#define MPLL_FOUT_SEL_SHIFT 4 > +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit > position*/ +#define TIMEOUT_EPLL_LOCK 1000 > + > +#define AUDIO_0_RATIO_MASK 0x0f > +#define AUDIO_1_RATIO_MASK 0x0f > + > +#define AUDIO0_SEL_MASK 0xf > +#define AUDIO1_SEL_MASK 0xf > + > +#define CLK_SRC_SCLK_EPLL 0x7 > +#define CLK_SRC_MOUT_EPLL (1<<12) > +#define AUDIO_CLKMUX_ASS (1<<0) > + > +/* CON0 bit-fields */ > +#define EPLL_CON0_MDIV_MASK 0x1ff > +#define EPLL_CON0_PDIV_MASK 0x3f > +#define EPLL_CON0_SDIV_MASK 0x7 > +#define EPLL_CON0_MDIV_SHIFT 16 > +#define EPLL_CON0_PDIV_SHIFT 8 > +#define EPLL_CON0_SDIV_SHIFT 0 > +#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 > +#define EPLL_CON0_LOCK_DET_EN_MASK 1 > + > +#define MPLL_FOUT_SEL_MASK 0x1 > +#define BPLL_FOUT_SEL_SHIFT 0 > +#define BPLL_FOUT_SEL_MASK 0x1 > +#endif > diff --git a/configs/odroid-xu3_defconfig > b/configs/odroid-xu3_defconfig new file mode 100644 > index 0000000..74aa0cf > --- /dev/null > +++ b/configs/odroid-xu3_defconfig > @@ -0,0 +1,4 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_EXYNOS=y > +CONFIG_TARGET_ODROID_XU3=y > +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" > diff --git a/include/configs/odroid_xu3.h > b/include/configs/odroid_xu3.h new file mode 100644 > index 0000000..867ac74 > --- /dev/null > +++ b/include/configs/odroid_xu3.h > @@ -0,0 +1,73 @@ > +/* > + * Copyright (C) 2013 Samsung Electronics > + * Hyungwon Hwang <human.hwang@samsung.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __CONFIG_ODROID_XU3_H > +#define __CONFIG_ODROID_XU3_H > + > +#include "exynos5-common.h" > + > +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " > +#define CONFIG_IDENT_STRING " for ODROID-XU3" > + > +#define CONFIG_OF_CONTROL > +#define CONFIG_BOARD_COMMON It is now possible to specify those two CONFIGs in odroidxu3_defconfig using Kconfig (board/samsung/odroid/setup.h). > + > +#define CONFIG_SYS_SDRAM_BASE 0x40000000 > +#define CONFIG_SYS_TEXT_BASE 0x43E00000 > + > +/* select serial console configuration */ > +#define CONFIG_SERIAL2 /* use SERIAL 2 */ > + > +#define TZPC_BASE_OFFSET 0x10000 > + > +#define CONFIG_CMD_MMC > +#define CONFIG_CMD_EXT2 > +#define CONFIG_CMD_FAT > + > +/* > + * FIXME: The number of bank is actually 8. But there is no way to > reserver the > + * last 16 Mib in the last bank now. So I just excluded the last bank > + * temporally. > + */ > +#define CONFIG_NR_DRAM_BANKS 7 > +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 > MB */ + > +#define CONFIG_ENV_IS_IN_MMC > + > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - > 0x1000000) + > +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ > +#undef CONFIG_EXYNOS_TMU > +#undef CONFIG_TMU_CMD_DTT > + > +#undef CONFIG_EXYNOS_SPL > +#undef CONFIG_SILENT_CONSOLE > +#undef CONFIG_CROS_EC > +#undef CONFIG_CROS_EC_SPI > +#undef CONFIG_CROS_EC_I2C > +#undef CONFIG_CROS_EC_KEYB > +#undef CONFIG_CMD_CROS_EC > +#undef CONFIG_KEYBOARD > +#undef CONFIG_SPI_BOOTING > +#undef CONFIG_ENV_IS_IN_SPI_FLASH > +#undef CONFIG_SPI_FLASH > +#undef CONFIG_EXYNOS_SPI > +#undef CONFIG_CMD_SF > +#undef CONFIG_CMD_SPI > +#undef CONFIG_SPI_FLASH_WINBOND > +#undef CONFIG_SPI_FLASH_GIGADEVICE > +#undef CONFIG_OF_SPI > +#undef CONFIG_FIT_BEST_MATCH > +#undef CONFIG_USB_BOOTING > +#undef CONFIG_CMD_NET > +#undef CONFIG_SMC911X > +#undef CONFIG_CMD_PXE > +#undef CONFIG_MENU > +#undef CONFIG_ENV_IS_IN_SPI_FLASH > + > + > +#endif /* __CONFIG_H */ -- Best regards, Lukasz Majewski Samsung R&D Institute Poland (SRPOL) | Linux Platform Group ^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board 2014-10-31 12:14 [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Hyungwon Hwang ` (3 preceding siblings ...) 2014-10-31 12:14 ` [U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3 Hyungwon Hwang @ 2014-11-04 5:07 ` Jaehoon Chung 4 siblings, 0 replies; 13+ messages in thread From: Jaehoon Chung @ 2014-11-04 5:07 UTC (permalink / raw) To: u-boot When you sent the patch vX, add the changelog. I don't know what changed at your patch V2. Best Regards, Jaehoon Chung On 10/31/2014 09:14 PM, Hyungwon Hwang wrote: > This patchset adds support for Exynos5422 odroid xu3 board. > I have done this work on the patchset submitted by Akshay Saraswat. > > https://patchwork.ozlabs.org/patch/400043/ > > Hyungwon Hwang (4): > exynos5: fix GPIO information of exynos5420 > Exynos5800: Add support for Exynos5800 > odroid: make some macros common > Odroid-XU3: Add support for Odroid-XU3 > > arch/arm/cpu/armv7/exynos/Kconfig | 4 + > arch/arm/dts/Makefile | 3 +- > arch/arm/dts/exynos5422-odroidxu3.dts | 72 +++++++++ > arch/arm/include/asm/arch-exynos/cpu.h | 11 +- > arch/arm/include/asm/arch-exynos/gpio.h | 261 +++++++++++++++++--------------- > board/samsung/odroid-xu3/Kconfig | 12 ++ > board/samsung/odroid-xu3/MAINTAINERS | 6 + > board/samsung/odroid-xu3/Makefile | 7 + > board/samsung/odroid-xu3/odroid-xu3.c | 132 ++++++++++++++++ > board/samsung/odroid-xu3/setup.h | 115 ++++++++++++++ > board/samsung/odroid/odroid.c | 1 + > board/samsung/odroid/setup.h | 8 - > configs/odroid-xu3_defconfig | 4 + > drivers/gpio/s5p_gpio.c | 4 +- > include/configs/odroid_xu3.h | 73 +++++++++ > 15 files changed, 576 insertions(+), 137 deletions(-) > create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts > create mode 100644 board/samsung/odroid-xu3/Kconfig > create mode 100644 board/samsung/odroid-xu3/MAINTAINERS > create mode 100644 board/samsung/odroid-xu3/Makefile > create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c > create mode 100644 board/samsung/odroid-xu3/setup.h > create mode 100644 configs/odroid-xu3_defconfig > create mode 100644 include/configs/odroid_xu3.h > ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2014-11-04 10:56 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2014-10-31 12:14 [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 1/4] exynos5: fix GPIO information of exynos5420 Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800 Hyungwon Hwang 2014-11-03 8:34 ` Lukasz Majewski 2014-11-04 1:26 ` Hyungwon Hwang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 3/4] odroid: make some macros common Hyungwon Hwang 2014-11-03 8:51 ` Lukasz Majewski 2014-11-04 1:49 ` Hyungwon Hwang 2014-11-04 8:29 ` Lukasz Majewski 2014-11-04 10:56 ` Minkyu Kang 2014-10-31 12:14 ` [U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3 Hyungwon Hwang 2014-11-03 9:09 ` Lukasz Majewski 2014-11-04 5:07 ` [U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board Jaehoon Chung
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