From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
To: Jiang Liu <jiang.liu@linux.intel.com>, <marc.zyngier@arm.com>,
<mark.rutland@arm.com>, <jason@lakedaemon.net>,
<tglx@linutronix.de>
Cc: <Catalin.Marinas@arm.com>, <Will.Deacon@arm.com>,
<liviu.dudau@arm.com>, <Harish.Kasiviswanathan@amd.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-doc@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)
Date: Tue, 4 Nov 2014 11:00:31 -0600 [thread overview]
Message-ID: <5459062F.6090603@amd.com> (raw)
In-Reply-To: <5458CE31.3040404@linux.intel.com>
On 11/4/14 07:01, Jiang Liu wrote:
> Hi Suravee,
> You may build a two level hierarchy irqdomains. Use the
> utilities in this thread
> http://www.spinics.net/lists/arm-kernel/msg374722.html to build an MSI
> irqdomain to manage MSI controllers
> in PCI devices. And build another irqdomain to manage SPI allocation
> in GICv2.
> That is: MSI irqdomain (program MSI registers) -->
> GIV irqdomain (manage SPIs in GICv2 controller)
That's great. I'll look at this patch in and make use of it to create to
MSI domain.
Thanks,
Suravee
> Regards!
> Gerry
WARNING: multiple messages have this Message-ID (diff)
From: Suravee.Suthikulpanit@amd.com (Suravee Suthikulpanit)
To: linux-arm-kernel@lists.infradead.org
Subject: [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)
Date: Tue, 4 Nov 2014 11:00:31 -0600 [thread overview]
Message-ID: <5459062F.6090603@amd.com> (raw)
In-Reply-To: <5458CE31.3040404@linux.intel.com>
On 11/4/14 07:01, Jiang Liu wrote:
> Hi Suravee,
> You may build a two level hierarchy irqdomains. Use the
> utilities in this thread
> http://www.spinics.net/lists/arm-kernel/msg374722.html to build an MSI
> irqdomain to manage MSI controllers
> in PCI devices. And build another irqdomain to manage SPI allocation
> in GICv2.
> That is: MSI irqdomain (program MSI registers) -->
> GIV irqdomain (manage SPIs in GICv2 controller)
That's great. I'll look at this patch in and make use of it to create to
MSI domain.
Thanks,
Suravee
> Regards!
> Gerry
WARNING: multiple messages have this Message-ID (diff)
From: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
To: Jiang Liu <jiang.liu@linux.intel.com>,
marc.zyngier@arm.com, mark.rutland@arm.com, jason@lakedaemon.net,
tglx@linutronix.de
Cc: Catalin.Marinas@arm.com, Will.Deacon@arm.com,
liviu.dudau@arm.com, Harish.Kasiviswanathan@amd.com,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)
Date: Tue, 4 Nov 2014 11:00:31 -0600 [thread overview]
Message-ID: <5459062F.6090603@amd.com> (raw)
In-Reply-To: <5458CE31.3040404@linux.intel.com>
On 11/4/14 07:01, Jiang Liu wrote:
> Hi Suravee,
> You may build a two level hierarchy irqdomains. Use the
> utilities in this thread
> http://www.spinics.net/lists/arm-kernel/msg374722.html to build an MSI
> irqdomain to manage MSI controllers
> in PCI devices. And build another irqdomain to manage SPI allocation
> in GICv2.
> That is: MSI irqdomain (program MSI registers) -->
> GIV irqdomain (manage SPIs in GICv2 controller)
That's great. I'll look at this patch in and make use of it to create to
MSI domain.
Thanks,
Suravee
> Regards!
> Gerry
next prev parent reply other threads:[~2014-11-04 17:00 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-03 22:16 [V10 PATCH 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support suravee.suthikulpanit
2014-11-03 22:16 ` suravee.suthikulpanit
2014-11-03 22:16 ` suravee.suthikulpanit at amd.com
2014-11-03 22:16 ` [V10 PATCH 1/2] genirq: Add irq_chip_set_type_parent function suravee.suthikulpanit
2014-11-03 22:16 ` suravee.suthikulpanit-5C7GfCeVMHo
2014-11-03 22:16 ` suravee.suthikulpanit at amd.com
2014-11-03 22:16 ` [V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X) suravee.suthikulpanit
2014-11-03 22:16 ` suravee.suthikulpanit
2014-11-03 22:16 ` suravee.suthikulpanit at amd.com
2014-11-03 22:51 ` Thomas Gleixner
2014-11-03 22:51 ` Thomas Gleixner
2014-11-04 3:22 ` Suravee Suthikulanit
2014-11-04 3:22 ` Suravee Suthikulanit
2014-11-04 3:22 ` Suravee Suthikulanit
2014-11-04 10:06 ` Thomas Gleixner
2014-11-04 10:06 ` Thomas Gleixner
2014-11-04 14:20 ` Suravee Suthikulpanit
2014-11-04 14:20 ` Suravee Suthikulpanit
2014-11-04 14:20 ` Suravee Suthikulpanit
2014-11-04 14:28 ` Thomas Gleixner
2014-11-04 14:28 ` Thomas Gleixner
2014-11-04 17:46 ` Marc Zyngier
2014-11-04 17:46 ` Marc Zyngier
2014-11-04 17:46 ` Marc Zyngier
2014-11-04 13:01 ` Jiang Liu
2014-11-04 13:01 ` Jiang Liu
2014-11-04 17:00 ` Suravee Suthikulpanit [this message]
2014-11-04 17:00 ` Suravee Suthikulpanit
2014-11-04 17:00 ` Suravee Suthikulpanit
2014-11-06 0:05 ` Suravee Suthikulanit
2014-11-06 0:05 ` Suravee Suthikulanit
2014-11-06 0:05 ` Suravee Suthikulanit
2014-11-06 0:23 ` Suravee Suthikulanit
2014-11-06 0:23 ` Suravee Suthikulanit
2014-11-06 0:23 ` Suravee Suthikulanit
2014-11-06 0:49 ` Thomas Gleixner
2014-11-06 0:49 ` Thomas Gleixner
2014-11-06 10:42 ` Thomas Gleixner
2014-11-06 10:42 ` Thomas Gleixner
2014-11-06 16:34 ` Marc Zyngier
2014-11-06 16:34 ` Marc Zyngier
2014-11-07 1:00 ` Jiang Liu
2014-11-07 1:00 ` Jiang Liu
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