From: Alexandre Courbot <acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Mikko Perttunen <mikko.perttunen-/1wQRMveznE@public.gmane.org>,
swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org,
gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org,
Mikko Perttunen
<mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH v4 REPOST 5/5] ARM: tegra: Add thermal reset (thermtrip) support to PMC
Date: Tue, 11 Nov 2014 15:21:15 +0900 [thread overview]
Message-ID: <5461AADB.2060207@nvidia.com> (raw)
In-Reply-To: <1415625137-4791-6-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org>
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
> @@ -606,6 +623,234 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
> }
> #endif
>
> +static const char * const tegra20_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "cpu",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> +};
> +
> +static const struct tegra_pmc_soc tegra20_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra20_powergates),
> + .powergates = tegra20_powergates,
> + .num_cpu_powergates = 0,
> + .cpu_powergates = NULL,
> +};
> +
> +static const char * const tegra30_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "cpu0",
> + [TEGRA_POWERGATE_3D] = "3d0",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_SATA] = "sata",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_3D1] = "3d1",
> +};
> +
> +static const u8 tegra30_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra30_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra30_powergates),
> + .powergates = tegra30_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
> + .cpu_powergates = tegra30_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const char * const tegra114_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "crail",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_CPU0] = "cpu0",
> + [TEGRA_POWERGATE_C0NC] = "c0nc",
> + [TEGRA_POWERGATE_C1NC] = "c1nc",
> + [TEGRA_POWERGATE_DIS] = "dis",
> + [TEGRA_POWERGATE_DISB] = "disb",
> + [TEGRA_POWERGATE_XUSBA] = "xusba",
> + [TEGRA_POWERGATE_XUSBB] = "xusbb",
> + [TEGRA_POWERGATE_XUSBC] = "xusbc",
> +};
> +
> +static const u8 tegra114_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU0,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra114_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra114_powergates),
> + .powergates = tegra114_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
> + .cpu_powergates = tegra114_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const char * const tegra124_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "crail",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_SATA] = "sata",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_CPU0] = "cpu0",
> + [TEGRA_POWERGATE_C0NC] = "c0nc",
> + [TEGRA_POWERGATE_C1NC] = "c1nc",
> + [TEGRA_POWERGATE_SOR] = "sor",
> + [TEGRA_POWERGATE_DIS] = "dis",
> + [TEGRA_POWERGATE_DISB] = "disb",
> + [TEGRA_POWERGATE_XUSBA] = "xusba",
> + [TEGRA_POWERGATE_XUSBB] = "xusbb",
> + [TEGRA_POWERGATE_XUSBC] = "xusbc",
> + [TEGRA_POWERGATE_VIC] = "vic",
> + [TEGRA_POWERGATE_IRAM] = "iram",
> +};
> +
> +static const u8 tegra124_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU0,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra124_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra124_powergates),
> + .powergates = tegra124_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
> + .cpu_powergates = tegra124_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const struct of_device_id tegra_pmc_match[] = {
> + { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
> + { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
> + { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
> + { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
> + { }
> +};
Is there a need for moving this huge block of declarations? AFAICT you
are only using tegra_pmc_match in your function, maybe you can just do a
forward declaration so does not get longer and more complex than it
needs to be?
This detail aside, patch looks ok to me.
WARNING: multiple messages have this Message-ID (diff)
From: acourbot@nvidia.com (Alexandre Courbot)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 REPOST 5/5] ARM: tegra: Add thermal reset (thermtrip) support to PMC
Date: Tue, 11 Nov 2014 15:21:15 +0900 [thread overview]
Message-ID: <5461AADB.2060207@nvidia.com> (raw)
In-Reply-To: <1415625137-4791-6-git-send-email-mikko.perttunen@kapsi.fi>
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
> @@ -606,6 +623,234 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
> }
> #endif
>
> +static const char * const tegra20_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "cpu",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> +};
> +
> +static const struct tegra_pmc_soc tegra20_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra20_powergates),
> + .powergates = tegra20_powergates,
> + .num_cpu_powergates = 0,
> + .cpu_powergates = NULL,
> +};
> +
> +static const char * const tegra30_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "cpu0",
> + [TEGRA_POWERGATE_3D] = "3d0",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_SATA] = "sata",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_3D1] = "3d1",
> +};
> +
> +static const u8 tegra30_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra30_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra30_powergates),
> + .powergates = tegra30_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
> + .cpu_powergates = tegra30_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const char * const tegra114_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "crail",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_CPU0] = "cpu0",
> + [TEGRA_POWERGATE_C0NC] = "c0nc",
> + [TEGRA_POWERGATE_C1NC] = "c1nc",
> + [TEGRA_POWERGATE_DIS] = "dis",
> + [TEGRA_POWERGATE_DISB] = "disb",
> + [TEGRA_POWERGATE_XUSBA] = "xusba",
> + [TEGRA_POWERGATE_XUSBB] = "xusbb",
> + [TEGRA_POWERGATE_XUSBC] = "xusbc",
> +};
> +
> +static const u8 tegra114_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU0,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra114_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra114_powergates),
> + .powergates = tegra114_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
> + .cpu_powergates = tegra114_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const char * const tegra124_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "crail",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_SATA] = "sata",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_CPU0] = "cpu0",
> + [TEGRA_POWERGATE_C0NC] = "c0nc",
> + [TEGRA_POWERGATE_C1NC] = "c1nc",
> + [TEGRA_POWERGATE_SOR] = "sor",
> + [TEGRA_POWERGATE_DIS] = "dis",
> + [TEGRA_POWERGATE_DISB] = "disb",
> + [TEGRA_POWERGATE_XUSBA] = "xusba",
> + [TEGRA_POWERGATE_XUSBB] = "xusbb",
> + [TEGRA_POWERGATE_XUSBC] = "xusbc",
> + [TEGRA_POWERGATE_VIC] = "vic",
> + [TEGRA_POWERGATE_IRAM] = "iram",
> +};
> +
> +static const u8 tegra124_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU0,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra124_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra124_powergates),
> + .powergates = tegra124_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
> + .cpu_powergates = tegra124_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const struct of_device_id tegra_pmc_match[] = {
> + { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
> + { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
> + { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
> + { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
> + { }
> +};
Is there a need for moving this huge block of declarations? AFAICT you
are only using tegra_pmc_match in your function, maybe you can just do a
forward declaration so does not get longer and more complex than it
needs to be?
This detail aside, patch looks ok to me.
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Courbot <acourbot@nvidia.com>
To: Mikko Perttunen <mikko.perttunen@kapsi.fi>,
<swarren@wwwdotorg.org>, <thierry.reding@gmail.com>,
<gnurou@gmail.com>
Cc: <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>, <wni@nvidia.com>,
Mikko Perttunen <mperttunen@nvidia.com>
Subject: Re: [PATCH v4 REPOST 5/5] ARM: tegra: Add thermal reset (thermtrip) support to PMC
Date: Tue, 11 Nov 2014 15:21:15 +0900 [thread overview]
Message-ID: <5461AADB.2060207@nvidia.com> (raw)
In-Reply-To: <1415625137-4791-6-git-send-email-mikko.perttunen@kapsi.fi>
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
> @@ -606,6 +623,234 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
> }
> #endif
>
> +static const char * const tegra20_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "cpu",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> +};
> +
> +static const struct tegra_pmc_soc tegra20_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra20_powergates),
> + .powergates = tegra20_powergates,
> + .num_cpu_powergates = 0,
> + .cpu_powergates = NULL,
> +};
> +
> +static const char * const tegra30_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "cpu0",
> + [TEGRA_POWERGATE_3D] = "3d0",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_SATA] = "sata",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_3D1] = "3d1",
> +};
> +
> +static const u8 tegra30_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra30_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra30_powergates),
> + .powergates = tegra30_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
> + .cpu_powergates = tegra30_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const char * const tegra114_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "crail",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_CPU0] = "cpu0",
> + [TEGRA_POWERGATE_C0NC] = "c0nc",
> + [TEGRA_POWERGATE_C1NC] = "c1nc",
> + [TEGRA_POWERGATE_DIS] = "dis",
> + [TEGRA_POWERGATE_DISB] = "disb",
> + [TEGRA_POWERGATE_XUSBA] = "xusba",
> + [TEGRA_POWERGATE_XUSBB] = "xusbb",
> + [TEGRA_POWERGATE_XUSBC] = "xusbc",
> +};
> +
> +static const u8 tegra114_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU0,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra114_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra114_powergates),
> + .powergates = tegra114_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
> + .cpu_powergates = tegra114_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const char * const tegra124_powergates[] = {
> + [TEGRA_POWERGATE_CPU] = "crail",
> + [TEGRA_POWERGATE_3D] = "3d",
> + [TEGRA_POWERGATE_VENC] = "venc",
> + [TEGRA_POWERGATE_PCIE] = "pcie",
> + [TEGRA_POWERGATE_VDEC] = "vdec",
> + [TEGRA_POWERGATE_L2] = "l2",
> + [TEGRA_POWERGATE_MPE] = "mpe",
> + [TEGRA_POWERGATE_HEG] = "heg",
> + [TEGRA_POWERGATE_SATA] = "sata",
> + [TEGRA_POWERGATE_CPU1] = "cpu1",
> + [TEGRA_POWERGATE_CPU2] = "cpu2",
> + [TEGRA_POWERGATE_CPU3] = "cpu3",
> + [TEGRA_POWERGATE_CELP] = "celp",
> + [TEGRA_POWERGATE_CPU0] = "cpu0",
> + [TEGRA_POWERGATE_C0NC] = "c0nc",
> + [TEGRA_POWERGATE_C1NC] = "c1nc",
> + [TEGRA_POWERGATE_SOR] = "sor",
> + [TEGRA_POWERGATE_DIS] = "dis",
> + [TEGRA_POWERGATE_DISB] = "disb",
> + [TEGRA_POWERGATE_XUSBA] = "xusba",
> + [TEGRA_POWERGATE_XUSBB] = "xusbb",
> + [TEGRA_POWERGATE_XUSBC] = "xusbc",
> + [TEGRA_POWERGATE_VIC] = "vic",
> + [TEGRA_POWERGATE_IRAM] = "iram",
> +};
> +
> +static const u8 tegra124_cpu_powergates[] = {
> + TEGRA_POWERGATE_CPU0,
> + TEGRA_POWERGATE_CPU1,
> + TEGRA_POWERGATE_CPU2,
> + TEGRA_POWERGATE_CPU3,
> +};
> +
> +static const struct tegra_pmc_soc tegra124_pmc_soc = {
> + .num_powergates = ARRAY_SIZE(tegra124_powergates),
> + .powergates = tegra124_powergates,
> + .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
> + .cpu_powergates = tegra124_cpu_powergates,
> + .has_tsense_reset = true,
> +};
> +
> +static const struct of_device_id tegra_pmc_match[] = {
> + { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
> + { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
> + { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
> + { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
> + { }
> +};
Is there a need for moving this huge block of declarations? AFAICT you
are only using tegra_pmc_match in your function, maybe you can just do a
forward declaration so does not get longer and more complex than it
needs to be?
This detail aside, patch looks ok to me.
next prev parent reply other threads:[~2014-11-11 6:21 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-10 13:12 [PATCH v4 REPOST 0/5] Thermal reset support in PMC Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
2014-11-10 13:12 ` [PATCH v4 REPOST 1/5] of: Add descriptions of thermtrip properties to Tegra PMC bindings Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
[not found] ` <1415625137-4791-2-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org>
2014-11-11 6:37 ` Alexandre Courbot
2014-11-11 6:37 ` Alexandre Courbot
2014-11-11 6:37 ` Alexandre Courbot
2014-11-12 12:07 ` Mikko Perttunen
2014-11-12 12:07 ` Mikko Perttunen
[not found] ` <54634D97.9050500-/1wQRMveznE@public.gmane.org>
2014-11-12 12:29 ` Thierry Reding
2014-11-12 12:29 ` Thierry Reding
2014-11-12 12:29 ` Thierry Reding
[not found] ` <20141112122951.GD30821-AwZRO8vwLAwmlAP/+Wk3EA@public.gmane.org>
2014-11-12 13:07 ` Mikko Perttunen
2014-11-12 13:07 ` Mikko Perttunen
2014-11-12 13:07 ` Mikko Perttunen
[not found] ` <54635B97.3030701-/1wQRMveznE@public.gmane.org>
2014-11-13 5:25 ` Alexandre Courbot
2014-11-13 5:25 ` Alexandre Courbot
2014-11-13 5:25 ` Alexandre Courbot
2014-11-10 13:12 ` [PATCH v4 REPOST 3/5] ARM: tegra124: Add I2C controller ids to device tree Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
2014-11-10 13:12 ` [PATCH v4 REPOST 4/5] ARM: tegra: Add PMC thermtrip programming to Jetson TK1 " Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
[not found] ` <1415625137-4791-1-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org>
2014-11-10 13:12 ` [PATCH v4 REPOST 2/5] of: Add nvidia,controller-id property to Tegra I2C bindings Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
2014-11-10 13:12 ` [PATCH v4 REPOST 2/5] of: Add nvidia, controller-id " Mikko Perttunen
2014-11-10 13:12 ` [PATCH v4 REPOST 5/5] ARM: tegra: Add thermal reset (thermtrip) support to PMC Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
2014-11-10 13:12 ` Mikko Perttunen
[not found] ` <1415625137-4791-6-git-send-email-mikko.perttunen-/1wQRMveznE@public.gmane.org>
2014-11-11 6:21 ` Alexandre Courbot [this message]
2014-11-11 6:21 ` Alexandre Courbot
2014-11-11 6:21 ` Alexandre Courbot
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