From: Alexander Graf <agraf@suse.de>
To: Tom Musta <tommusta@gmail.com>,
qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] target-ppc: Load/Store Vector Element Storage Alignment
Date: Thu, 20 Nov 2014 15:07:49 +0100 [thread overview]
Message-ID: <546DF5B5.5010807@suse.de> (raw)
In-Reply-To: <1416257911-17426-1-git-send-email-tommusta@gmail.com>
On 17.11.14 21:58, Tom Musta wrote:
> The Load Vector Element Indexed and Store Vector Element Indexed
> instructions compute an effective address in the usual manner.
> However, they truncate that address to the natural boundary.
> For example, the lvewx instruction will ignore the least significant
> two bits of the address and thus load the aligned word of storage.
>
> Fix the generators for these instruction to properly perform this
> truncation.
>
> Signed-off-by: Tom Musta <tommusta@gmail.com>
Thanks, applied to ppc-next-2.3
Alex
prev parent reply other threads:[~2014-11-20 14:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-17 20:58 [Qemu-devel] [PATCH] target-ppc: Load/Store Vector Element Storage Alignment Tom Musta
2014-11-20 14:07 ` Alexander Graf [this message]
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