From: Yijing Wang <wangyijing@huawei.com>
To: Jiang Liu <jiang.liu@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Will Deacon <will.deacon@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: Removal of bus->msi assignment breaks MSI with stacked domains
Date: Fri, 21 Nov 2014 11:46:31 +0800 [thread overview]
Message-ID: <546EB597.20806@huawei.com> (raw)
In-Reply-To: <546EA2AB.9080609@linux.intel.com>
On 2014/11/21 10:25, Jiang Liu wrote:
> On 2014/11/21 9:54, Yijing Wang wrote:
>>>> Thomas, let me know if you want to do that. I suppose we could add a new
>>>> patch to add it back, but that would leave bisection broken for the
>>>> interval between c167caf8d174 and the patch that adds it back.
>>>
>>> Fortunately my irq/irqdomain branch is not immutable yet. So we have
>>> no problem at that point. I can rebase on your branch until tomorrow
>>> night. Or just rebase on mainline and we sort out the merge conflicts
>>> later, i.e. delegate them to Linus so his job of pulling stuff gets
>>> not completely boring.
>>
>> Hi Thomas, sorry for my introducing the broken.
>>
>>>
>>> What I'm more worried about is whether this intended change is going
>>> to inflict a problem on Jiangs intention to deduce the MSI irq domain
>>> from the device, which we really need for making DMAR work w/o going
>>> through loops and hoops.
>>>
>>> I have limited knowledge about the actual scope of iommu (DMAR) units
>>> versus device/bus/host-controllers, so I would appreciate a proper
>>> explanation for that from you or Jiang or both.
>>
>> In my personal opinion, if it's not necessary, we should not put stuff
>> into pci_dev or pci_bus. If we plan to save msi_controller in pci_bus or
>> pci_dev.
>> I have a proposal, I would be appreciated if you could give some comments.
>> First we refactor pci_host_bridge to make a generic
>> pci_host_bridge, then we could save pci domain in it to eliminate
>> arch specific functions. I aslo wanted to save msi_controller as
>> pci domain, but now Jiang refactor hierarchy irq domain, and
>> pci devices under the same pci host bridge may need to associate
>> to different msi_controllers.
>>
>> So I want to associate a msi_controller finding ops with generic pci_host_bridge,
>> then every pci device could find its msi_controller/irq_domain by a
>> common function
>>
>> E.g
>>
>> struct msi_controller *pci_msi_controller(struct pci_dev *pdev)
>> {
>> struct msi_controller *ctrl;
>> struct pci_host_bridge *host = find_pci_host_bridge(pdev->bus);
>> if (host && host->pci_get_msi_controller)
>> ctrl = pci_host_bridge->pci_get_msi_controller(struct pci_dev *pdev);
>>
>> return ctrl;
>> }
> Hi Yijing,
> This may be a little overhead for x86 because we could get
> irqdomain from pci_dev itself through:
> pci_dev->dev.archdata.iommu->ir_msi_domain.
> This doesn't work currently because pci_dev->dev.archdata.iommu
> is set on the first dma mapping request, but we have a plan to set it
> when creating PCI devices so we don't need to search the iommu list
> at runtime.
> Even the whole msi_controller concept may be killed for x86.
> Actually I'm trying to convert all MSI arch code to use hierarchy
> irqdomain, then we don't need arch_setup_msi_irqs() and
> msi_controller.setup_irq() and related anymore. But the issue is
> that it affects too many architectures and may cause slightly code
> size increase.
> If we could convert all PCI MSI code to use hierarchy irqdomain,
> then the suggested interface is:
> struct irq_domain *pci_get_msi_irqdomain(struct pci_dev *pdev);
> Thoughts?
So the final solution depends the MSI refactoring work progress.
(glue layer)
I prefer pci_dev->msi_controller->(msi irq hierarchy domain)/(normal msi irq allocation code).
If we want to eliminate msi_controller, we must force all PCI MSI code to use hierarchy
irq domain. I doubt whether it is worth to do.
Thanks!
Yijing.
> Regards!
> Gerry
>>
>> If I miss something, please let me know, thanks.
>>
>> Thanks!
>> Yijing.
>>
>>
>>>
>>> My guts feeling tells me that anything less granular than the bus
>>> level is wrong and according to my limited knowledge Intel even has
>>> DMARs which are assigned to a single device it's even more wrong. So
>>> the proper change would be not to push it from bus to something above
>>> the bus, but instead make it a per device property.
>>>
>>> But my knowledge there is limited, so I rely on the PCI/architecture
>>> experts to sort that out.
>>>
>>> Let me know ASAP.
>>>
>>> Thanks,
>>>
>>> tglx
>>>
>>> .
>>>
>>
>>
>
> .
>
--
Thanks!
Yijing
WARNING: multiple messages have this Message-ID (diff)
From: wangyijing@huawei.com (Yijing Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: Removal of bus->msi assignment breaks MSI with stacked domains
Date: Fri, 21 Nov 2014 11:46:31 +0800 [thread overview]
Message-ID: <546EB597.20806@huawei.com> (raw)
In-Reply-To: <546EA2AB.9080609@linux.intel.com>
On 2014/11/21 10:25, Jiang Liu wrote:
> On 2014/11/21 9:54, Yijing Wang wrote:
>>>> Thomas, let me know if you want to do that. I suppose we could add a new
>>>> patch to add it back, but that would leave bisection broken for the
>>>> interval between c167caf8d174 and the patch that adds it back.
>>>
>>> Fortunately my irq/irqdomain branch is not immutable yet. So we have
>>> no problem at that point. I can rebase on your branch until tomorrow
>>> night. Or just rebase on mainline and we sort out the merge conflicts
>>> later, i.e. delegate them to Linus so his job of pulling stuff gets
>>> not completely boring.
>>
>> Hi Thomas, sorry for my introducing the broken.
>>
>>>
>>> What I'm more worried about is whether this intended change is going
>>> to inflict a problem on Jiangs intention to deduce the MSI irq domain
>>> from the device, which we really need for making DMAR work w/o going
>>> through loops and hoops.
>>>
>>> I have limited knowledge about the actual scope of iommu (DMAR) units
>>> versus device/bus/host-controllers, so I would appreciate a proper
>>> explanation for that from you or Jiang or both.
>>
>> In my personal opinion, if it's not necessary, we should not put stuff
>> into pci_dev or pci_bus. If we plan to save msi_controller in pci_bus or
>> pci_dev.
>> I have a proposal, I would be appreciated if you could give some comments.
>> First we refactor pci_host_bridge to make a generic
>> pci_host_bridge, then we could save pci domain in it to eliminate
>> arch specific functions. I aslo wanted to save msi_controller as
>> pci domain, but now Jiang refactor hierarchy irq domain, and
>> pci devices under the same pci host bridge may need to associate
>> to different msi_controllers.
>>
>> So I want to associate a msi_controller finding ops with generic pci_host_bridge,
>> then every pci device could find its msi_controller/irq_domain by a
>> common function
>>
>> E.g
>>
>> struct msi_controller *pci_msi_controller(struct pci_dev *pdev)
>> {
>> struct msi_controller *ctrl;
>> struct pci_host_bridge *host = find_pci_host_bridge(pdev->bus);
>> if (host && host->pci_get_msi_controller)
>> ctrl = pci_host_bridge->pci_get_msi_controller(struct pci_dev *pdev);
>>
>> return ctrl;
>> }
> Hi Yijing,
> This may be a little overhead for x86 because we could get
> irqdomain from pci_dev itself through:
> pci_dev->dev.archdata.iommu->ir_msi_domain.
> This doesn't work currently because pci_dev->dev.archdata.iommu
> is set on the first dma mapping request, but we have a plan to set it
> when creating PCI devices so we don't need to search the iommu list
> at runtime.
> Even the whole msi_controller concept may be killed for x86.
> Actually I'm trying to convert all MSI arch code to use hierarchy
> irqdomain, then we don't need arch_setup_msi_irqs() and
> msi_controller.setup_irq() and related anymore. But the issue is
> that it affects too many architectures and may cause slightly code
> size increase.
> If we could convert all PCI MSI code to use hierarchy irqdomain,
> then the suggested interface is:
> struct irq_domain *pci_get_msi_irqdomain(struct pci_dev *pdev);
> Thoughts?
So the final solution depends the MSI refactoring work progress.
(glue layer)
I prefer pci_dev->msi_controller->(msi irq hierarchy domain)/(normal msi irq allocation code).
If we want to eliminate msi_controller, we must force all PCI MSI code to use hierarchy
irq domain. I doubt whether it is worth to do.
Thanks!
Yijing.
> Regards!
> Gerry
>>
>> If I miss something, please let me know, thanks.
>>
>> Thanks!
>> Yijing.
>>
>>
>>>
>>> My guts feeling tells me that anything less granular than the bus
>>> level is wrong and according to my limited knowledge Intel even has
>>> DMARs which are assigned to a single device it's even more wrong. So
>>> the proper change would be not to push it from bus to something above
>>> the bus, but instead make it a per device property.
>>>
>>> But my knowledge there is limited, so I rely on the PCI/architecture
>>> experts to sort that out.
>>>
>>> Let me know ASAP.
>>>
>>> Thanks,
>>>
>>> tglx
>>>
>>> .
>>>
>>
>>
>
> .
>
--
Thanks!
Yijing
next prev parent reply other threads:[~2014-11-21 3:46 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-20 16:31 Removal of bus->msi assignment breaks MSI with stacked domains Marc Zyngier
2014-11-20 16:31 ` Marc Zyngier
2014-11-20 21:53 ` Bjorn Helgaas
2014-11-20 21:53 ` Bjorn Helgaas
2014-11-20 23:10 ` Thomas Gleixner
2014-11-20 23:10 ` Thomas Gleixner
2014-11-20 23:30 ` Bjorn Helgaas
2014-11-20 23:30 ` Bjorn Helgaas
2014-11-21 9:33 ` Marc Zyngier
2014-11-21 9:33 ` Marc Zyngier
2014-11-21 1:54 ` Yijing Wang
2014-11-21 1:54 ` Yijing Wang
2014-11-21 2:25 ` Jiang Liu
2014-11-21 2:25 ` Jiang Liu
2014-11-21 3:46 ` Yijing Wang [this message]
2014-11-21 3:46 ` Yijing Wang
2014-11-21 10:00 ` Marc Zyngier
2014-11-21 10:00 ` Marc Zyngier
2014-11-21 17:31 ` Bjorn Helgaas
2014-11-21 17:31 ` Bjorn Helgaas
2014-11-22 4:13 ` Yijing Wang
2014-11-22 4:13 ` Yijing Wang
2014-11-21 1:22 ` Yijing Wang
2014-11-21 1:22 ` Yijing Wang
2014-11-21 1:46 ` Thomas Gleixner
2014-11-21 1:46 ` Thomas Gleixner
2014-11-21 2:03 ` Jiang Liu
2014-11-21 2:03 ` Jiang Liu
2014-11-21 2:12 ` Yijing Wang
2014-11-21 2:12 ` Yijing Wang
2014-11-21 2:05 ` Yijing Wang
2014-11-21 2:05 ` Yijing Wang
2014-11-21 8:46 ` Lucas Stach
2014-11-21 8:46 ` Lucas Stach
2014-11-21 10:29 ` Marc Zyngier
2014-11-21 10:29 ` Marc Zyngier
2014-11-21 10:49 ` Thomas Gleixner
2014-11-21 10:49 ` Thomas Gleixner
2014-11-21 11:30 ` Marc Zyngier
2014-11-21 11:30 ` Marc Zyngier
2014-11-21 12:04 ` Yijing Wang
2014-11-21 12:04 ` Yijing Wang
2014-11-21 10:11 ` Marc Zyngier
2014-11-21 10:11 ` Marc Zyngier
2014-11-21 11:57 ` Yijing Wang
2014-11-21 11:57 ` Yijing Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=546EB597.20806@huawei.com \
--to=wangyijing@huawei.com \
--cc=bhelgaas@google.com \
--cc=catalin.marinas@arm.com \
--cc=jiang.liu@linux.intel.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=marc.zyngier@arm.com \
--cc=tglx@linutronix.de \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.