Re: [PATCH RESEND 1/7] clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi

[Sylwester Nawrocki <s.nawrocki@samsung.com>]

On 24/11/14 08:30, Andrzej Hajda wrote:
> sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock.
> The patch models this dependency using parent/child hirerarchy.
> 
> The patch fixes issue with system hangs during mixer device access, mixer uses
> sclk_hdmiphy descendant clock.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

I guess it can be merged as a bug fix, however it's not an ideal
solution. The proper approach would be probably to have the HDMIPHY
driver exposing a clk object. Unfortunately there seems to be
no sufficiently documented hardware control sequences available
for such a fine-grained hardware control.

> ---
>  drivers/clk/samsung/clk-exynos4.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
> index 940f028..88e8c6b 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -505,7 +505,7 @@ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata
>  /* fixed rate clocks generated inside the soc */
>  static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = {
>  	FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000),
> -	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000),
> +	FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", "hdmi", 0, 27000000),
>  	FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000),
>  };


-- 
Regards,
Sylwester