[U-Boot] [PATCH v9 1/2] Odroid-XU3: Add support for Odroid-XU3

[Jaehoon Chung <jh80.chung@samsung.com>]

On 11/27/2014 10:21 PM, Hyungwon Hwang wrote:
> This patch adds support for Odroid-XU3.
> 
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> Tested-by: Lukasz Majewski <l.majewski@samsung.com>
> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
> Cc: Minkyu Kang <mk7.kang@samsung.com>
> Cc: Lukasz Majewski <l.majewski@samsung.com>
> ---
> Changes for v3:
> - Remove unnecessary node from DT file
> - Remove unnecessary features from config file
> - Remove unnecessary macros from board-specific header file
> - Fix some trivial typos in comments
> 
> Changes for v4:
> - Add MMC FIFO buffer's configuration to DT file
> - Make CONFIG_OF_CONTROL be set by the target information
> - Add basic document to doc/README.odroid-xu3
> - Add CONFIG_CMD_EXT4 to config file
> - Add environment size and offset to config file
> - Add extra default environment to make bootable without modification
> - Remove unnecessary features from config file
> 
> Changes for v5:
> - Convert /include/ to #include in DT file
> 
> Changes for v6:
> - Separate out the documentation to new commit
> - Remove unnecessary header file inclusions from the board-specific setup file
> - Make the function board_clock_init be declared, only when
>   CONFIG_BOARD_EARLY_INIT_F is defined
> 
> Changes for v7:
> - Remove OF_CONTROL dependency from !SPL_BUILD
> 
> Changes for v8:
> - Remove unnecessary properties in DT mmc node
> 
> Changes for v9:
> - Remove useless variables in the default environment
> - Replace the detailed information to the reference to the documentation
> 
>  arch/arm/cpu/armv7/exynos/Kconfig     |   5 ++
>  arch/arm/dts/Makefile                 |   3 +-
>  arch/arm/dts/exynos5422-odroidxu3.dts |  57 +++++++++++++++
>  board/samsung/odroid-xu3/Kconfig      |  12 +++
>  board/samsung/odroid-xu3/MAINTAINERS  |   6 ++
>  board/samsung/odroid-xu3/Makefile     |   7 ++
>  board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++++++++++++++++
>  board/samsung/odroid-xu3/setup.h      |  95 ++++++++++++++++++++++++
>  configs/odroid-xu3_defconfig          |   4 +
>  include/configs/odroid.h              |   5 --
>  include/configs/odroid_xu3.h          | 133 ++++++++++++++++++++++++++++++++++
>  11 files changed, 443 insertions(+), 6 deletions(-)
>  create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
>  create mode 100644 board/samsung/odroid-xu3/Kconfig
>  create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
>  create mode 100644 board/samsung/odroid-xu3/Makefile
>  create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
>  create mode 100644 board/samsung/odroid-xu3/setup.h
>  create mode 100644 configs/odroid-xu3_defconfig
>  create mode 100644 include/configs/odroid_xu3.h
> 
> diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
> index 13dbd95..16c9a0e 100644
> --- a/arch/arm/cpu/armv7/exynos/Kconfig
> +++ b/arch/arm/cpu/armv7/exynos/Kconfig
> @@ -24,6 +24,10 @@ config TARGET_TRATS2
>  config TARGET_ODROID
>  	bool "Exynos4412 Odroid board"
>  
> +config TARGET_ODROID_XU3
> +	bool "Exynos5422 Odroid board"
> +	select OF_CONTROL
> +
>  config TARGET_ARNDALE
>  	bool "Exynos5250 Arndale board"
>  	select SUPPORT_SPL
> @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig"
>  source "board/samsung/origen/Kconfig"
>  source "board/samsung/trats2/Kconfig"
>  source "board/samsung/odroid/Kconfig"
> +source "board/samsung/odroid-xu3/Kconfig"
>  source "board/samsung/arndale/Kconfig"
>  source "board/samsung/smdk5250/Kconfig"
>  source "board/samsung/smdk5420/Kconfig"
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index e5846ea..a811b1b 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -13,7 +13,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
>  	exynos5250-smdk5250.dtb \
>  	exynos5420-smdk5420.dtb \
>  	exynos5420-peach-pit.dtb \
> -	exynos5800-peach-pi.dtb
> +	exynos5800-peach-pi.dtb \
> +	exynos5422-odroidxu3.dtb
>  dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
>  	tegra20-medcom-wide.dtb \
>  	tegra20-paz00.dtb \
> diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts
> new file mode 100644
> index 0000000..533d88e
> --- /dev/null
> +++ b/arch/arm/dts/exynos5422-odroidxu3.dts
> @@ -0,0 +1,57 @@
> +/*
> + * Odroid XU3 device tree source
> + *
> + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +/dts-v1/;
> +#include "exynos54xx.dtsi"
> +
> +/ {
> +	model = "Odroid XU3 based on EXYNOS5422";
> +	compatible = "samsung,odroidxu3", "samsung,exynos5";
> +
> +	aliases {
> +		serial0 = "/serial at 12C00000";
> +		console = "/serial at 12C20000";
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg =  <0x40000000 0x10000000
> +			0x50000000 0x10000000
> +			0x60000000 0x10000000
> +			0x70000000 0x10000000
> +			0x80000000 0x10000000
> +			0x90000000 0x10000000
> +			0xa0000000 0x10000000
> +			0xb0000000 0xea00000>;
> +	};
> +
> +	serial at 12C20000 {
> +		status="okay";
> +	};
> +
> +	mmc at 12200000 {
> +		samsung,bus-width = <8>;
> +		samsung,timing = <1 3 3>;
> +		fifoth_val = <0x200f0020>;

If you resend the patch, i want to change the fifoth_val from 0x200f0020 to 0x201f0020.
(Well, i'm not sure what's right. but when i have checked, the fifoth_depth is 0x40.
Then Rx_MASK = FIFOTH_DEPTH/2 - 1, TX_MASK = FIFOTH_DEPTH/2.

> +	};
> +
> +	mmc at 12210000 {
> +		status = "disabled";
> +	};
> +
> +	mmc at 12220000 {
> +		samsung,bus-width = <4>;
> +		samsung,timing = <1 2 3>;
> +		fifoth_val = <0x200f0020>;

Ditto.

> +	};
> +
> +	mmc at 12230000 {
> +		status = "disabled";
> +	};
> +};
> diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig
> new file mode 100644
> index 0000000..6159692
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_ODROID_XU3
> +
> +config SYS_BOARD
> +	default "odroid-xu3"
> +
> +config SYS_VENDOR
> +	default "samsung"
> +
> +config SYS_CONFIG_NAME
> +	default "odroid_xu3"
> +
> +endif
> diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS
> new file mode 100644
> index 0000000..50cf928
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/MAINTAINERS
> @@ -0,0 +1,6 @@
> +ODROID-XU3 BOARD
> +M:	Hyungwon Hwang <human.hwang@samsung.com>
> +S:	Maintained
> +F:	board/samsung/odroid-xu3/
> +F:	include/configs/odroid_xu3.h
> +F:	configs/odroid-xu3_defconfig
> diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile
> new file mode 100644
> index 0000000..85ae5c5
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved.
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y	:= odroid-xu3.o
> diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c
> new file mode 100644
> index 0000000..8c54842
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/odroid-xu3.c
> @@ -0,0 +1,122 @@
> +/*
> + * Copyright (C) 2014 Samsung Electronics
> + * Hyungwon Hwang <human.hwang@samsung.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/clock.h>
> +#include "setup.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +unsigned int get_board_rev(void)
> +{
> +	return 0;
> +}
> +
> +int exynos_init(void)
> +{
> +	return 0;
> +}
> +
> +#ifdef CONFIG_BOARD_EARLY_INIT_F
> +static int board_clock_init(void)
> +{
> +	unsigned int set, clr, clr_src_cpu, clr_pll_con0;
> +	struct exynos5420_clock *clk = (struct exynos5420_clock *)
> +						samsung_get_base_clock();
> +	/*
> +	 * CMU_CPU clocks src to MPLL
> +	 * Bit values:                 0  ; 1
> +	 * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
> +	 * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
> +	 * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
> +	 * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
> +	*/
> +
> +	/* Set CMU_CPU clocks src to OSCCLK */
> +	clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);
> +	set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);
> +
> +	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> +
> +	while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
> +		continue;
> +
> +	/* Set APLL to 1200MHz */
> +	clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |
> +			PLL_ENABLE(1);
> +	set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);
> +
> +	clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
> +
> +	while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
> +		continue;
> +
> +	/* Set CMU_CPU clocks src to APLL */
> +	set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);
> +	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
> +
> +	while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))
> +		continue;
> +
> +	clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |
> +	      PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);
> +	set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |
> +	      PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);
> +
> +	clrsetbits_le32(&clk->div_cpu0, clr, set);
> +
> +	while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
> +		continue;
> +
> +	/* Set MPLL to 800MHz */
> +	set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);
> +
> +	clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
> +
> +	while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
> +		continue;
> +
> +	/* Set CLKMUX_UART src to MPLL */
> +	clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7);
> +	set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3);
> +
> +	clrsetbits_le32(&clk->src_peric0, clr, set);
> +
> +	/* Set SCLK_UART to 400 MHz (MPLL / 2) */
> +	clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
> +	      UART3_RATIO(15);
> +	set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |
> +	      UART3_RATIO(1);
> +
> +	clrsetbits_le32(&clk->div_peric0, clr, set);
> +
> +	while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING)
> +		continue;
> +
> +	/* Set CLKMUX_MMC src to MPLL */
> +	clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);
> +	set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);
> +
> +	clrsetbits_le32(&clk->src_fsys, clr, set);
> +
> +	clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff);
> +	set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);
> +
> +	clrsetbits_le32(&clk->div_fsys1, clr, set);
> +
> +	/* Wait for divider ready status */
> +	while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
> +		continue;
> +
> +	return 0;
> +}
> +
> +int exynos_early_init_f(void)
> +{
> +	return board_clock_init();
> +}
> +#endif
> diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h
> new file mode 100644
> index 0000000..143c189
> --- /dev/null
> +++ b/board/samsung/odroid-xu3/setup.h
> @@ -0,0 +1,95 @@
> +/*
> + * (C) Copyright 2014 Samsung Electronics
> + * Hyungwon Hwang <human.hwang@samsung.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#ifndef __ODROID_XU3_SETUP__
> +#define __ODROID_XU3_SETUP__
> +
> +#define SDIV(x)                 ((x) & 0x7)
> +#define PDIV(x)                 (((x) & 0x3f) << 8)
> +#define MDIV(x)                 (((x) & 0x3ff) << 16)
> +#define FSEL(x)                 (((x) & 0x1) << 27)
> +#define PLL_LOCKED_BIT          (0x1 << 29)
> +#define PLL_ENABLE(x)           (((x) & 0x1) << 31)
> +
> +/* CLK_SRC_CPU */
> +#define MUX_APLL_SEL(x)         ((x) & 0x1)
> +#define MUX_CORE_SEL(x)         (((x) & 0x1) << 16)
> +
> +/* CLK_MUX_STAT_CPU */
> +#define APLL_SEL(x)             ((x) & 0x7)
> +#define CORE_SEL(x)             (((x) & 0x7) << 16)
> +#define MUX_STAT_CPU_CHANGING(x)	!(((x) & APLL_SEL(0)) ||	\
> +					   (x) & APLL_SEL(1) ||		\
> +					   (x) & CORE_SEL(0) ||		\
> +					   (x) & CORE_SEL(1))
> +
> +/* CLK_DIV_CPU0 */
> +#define ARM_RATIO(x)           ((x) & 0x7)
> +#define CPUD_RATIO(x)         (((x) & 0x7) << 4)
> +#define ATB_RATIO(x)         (((x) & 0x7) << 16)
> +#define PCLK_DBG_RATIO(x)       (((x) & 0x7) << 20)
> +#define APLL_RATIO(x)           (((x) & 0x7) << 24)
> +#define ARM2_RATIO(x)         (((x) & 0x7) << 28)
> +
> +/* CLK_DIV_STAT_CPU0 */
> +#define DIV_CPUD(x)           (((x) & 0x1) << 4)
> +#define DIV_ATB(x)              (((x) & 0x1) << 16)
> +#define DIV_PCLK_DBG(x)         (((x) & 0x1) << 20)
> +#define DIV_APLL(x)             (((x) & 0x1) << 24)
> +#define DIV_ARM2(x)            (((x) & 0x1) << 28)
> +
> +#define DIV_STAT_CHANGING	0x1
> +#define DIV_STAT_CPU0_CHANGING  (DIV_CPUD(DIV_STAT_CHANGING) | \
> +				 DIV_ATB(DIV_STAT_CHANGING) | \
> +				 DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
> +				 DIV_APLL(DIV_STAT_CHANGING) | \
> +				 DIV_ARM2(DIV_STAT_CHANGING))
> +
> +/* Set CLK_SRC_PERIC0 */
> +#define UART0_SEL(x)		(((x) & 0xf) << 4)
> +#define UART1_SEL(x)		(((x) & 0xf) << 8)
> +#define UART2_SEL(x)		(((x) & 0xf) << 12)
> +#define UART3_SEL(x)		(((x) & 0xf) << 16)
> +
> +/* Set CLK_DIV_PERIC0 */
> +#define UART0_RATIO(x)		(((x) & 0xf) << 8)
> +#define UART1_RATIO(x)		(((x) & 0xf) << 12)
> +#define UART2_RATIO(x)		(((x) & 0xf) << 16)
> +#define UART3_RATIO(x)		(((x) & 0xf) << 20)
> +
> +/* Set CLK_DIV_STAT_PERIC0 */
> +#define DIV_UART0(x)		((x) & 0x1)
> +#define DIV_UART1(x)		(((x) & 0x1) << 4)
> +#define DIV_UART2(x)		(((x) & 0x1) << 8)
> +#define DIV_UART3(x)		(((x) & 0x1) << 12)
> +#define DIV_UART4(x)		(((x) & 0x1) << 16)
> +
> +#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
> +				  DIV_UART3(DIV_STAT_CHANGING) | \
> +				  DIV_UART2(DIV_STAT_CHANGING) | \
> +				  DIV_UART1(DIV_STAT_CHANGING) | \
> +				  DIV_UART0(DIV_STAT_CHANGING))
> +
> +/* CLK_SRC_FSYS */
> +#define MUX_MMC0_SEL(x)		(((x) & 0x7) << 8)
> +#define MUX_MMC1_SEL(x)		(((x) & 0x7) << 12)
> +#define MUX_MMC2_SEL(x)		(((x) & 0x7) << 16)
> +
> +/* CLK_DIV_FSYS1 */
> +#define MMC0_RATIO(x)		((x) & 0x3ff)
> +#define MMC1_RATIO(x)		(((x) & 0x3ff) << 10)
> +#define MMC2_RATIO(x)		(((x) & 0x3ff) << 20)
> +
> +#define DIV_MMC0(x)		(((x) & 1) << 20)
> +#define DIV_MMC1(x)		(((x) & 1) << 24)
> +#define DIV_MMC2(x)		(((x) & 1) << 28)
> +
> +#define DIV_STAT_FSYS1_CHANGING	(DIV_MMC0(DIV_STAT_CHANGING) | \
> +				 DIV_MMC1(DIV_STAT_CHANGING) | \
> +				 DIV_MMC2(DIV_STAT_CHANGING))
> +
> +#endif
> diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
> new file mode 100644
> index 0000000..74aa0cf
> --- /dev/null
> +++ b/configs/odroid-xu3_defconfig
> @@ -0,0 +1,4 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_EXYNOS=y
> +CONFIG_TARGET_ODROID_XU3=y
> +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
> diff --git a/include/configs/odroid.h b/include/configs/odroid.h
> index 807e96b..660b6ae 100644
> --- a/include/configs/odroid.h
> +++ b/include/configs/odroid.h
> @@ -166,11 +166,6 @@
>  	"mmcbootpart=1\0" \
>  	"mmcrootdev=0\0" \
>  	"mmcrootpart=2\0" \
> -	"bootdelay=0\0" \
> -	"dfu_alt_system="CONFIG_DFU_ALT \
> -	"dfu_alt_info=Please reset the board\0" \
> -	"consoleon=set console console=ttySAC1,115200n8; save; reset\0" \
> -	"consoleoff=set console console=ram; save; reset\0" \
>  	"initrdname=uInitrd\0" \
>  	"initrdaddr=42000000\0" \
>  	"fdtaddr=40800000\0"

This is not XU3, separate the patch.

> diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
> new file mode 100644
> index 0000000..1d53653
> --- /dev/null
> +++ b/include/configs/odroid_xu3.h
> @@ -0,0 +1,133 @@
> +/*
> + * Copyright (C) 2013 Samsung Electronics
> + * Hyungwon Hwang <human.hwang@samsung.com>
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_ODROID_XU3_H
> +#define __CONFIG_ODROID_XU3_H
> +
> +#include "exynos5-common.h"
> +
> +#define CONFIG_SYS_PROMPT		"ODROID-XU3 # "
> +#define CONFIG_IDENT_STRING		" for ODROID-XU3"
> +
> +#define CONFIG_BOARD_COMMON
> +
> +#define CONFIG_SYS_SDRAM_BASE		0x40000000
> +#define CONFIG_SYS_TEXT_BASE		0x43E00000
> +
> +/* select serial console configuration */
> +#define CONFIG_SERIAL2			/* use SERIAL 2 */
> +
> +#define TZPC_BASE_OFFSET		0x10000
> +
> +#define CONFIG_CMD_MMC
> +#define CONFIG_CMD_EXT2
> +#define CONFIG_CMD_EXT4
> +#define CONFIG_CMD_FAT
> +
> +/*
> + * FIXME: The number of bank is actually 8. But there is no way to reserver the
> + * last 16 Mib in the last bank now. So I just excluded the last bank
> + * temporally.
> + */
> +#define CONFIG_NR_DRAM_BANKS	7
> +#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
> +
> +#define CONFIG_ENV_IS_IN_MMC
> +
> +#undef CONFIG_ENV_SIZE
> +#undef CONFIG_ENV_OFFSET
> +#define CONFIG_ENV_SIZE			4096
> +#define CONFIG_ENV_OFFSET		(SZ_1K * 1280) /* 1.25 MiB offset */
> +
> +#define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_LOAD_ADDR - 0x1000000)
> +
> +#define CONFIG_BOOTCOMMAND		"run autoboot"
> +#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
> +
> +/*
> + * For details, refer the documentation: doc/README.odroid
> +*/
> +#ifdef CONFIG_EXTRA_ENV_SETTINGS
> +#undef CONFIG_EXTRA_ENV_SETTINGS
> +#endif
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	"loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \
> +		"${kernelname}\0" \
> +	"loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \
> +		"${initrdname}\0" \
> +	"loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \
> +		"${fdtfile}\0" \
> +	"check_ramdisk=" \
> +		"if run loadinitrd; then " \
> +			"setenv initrd_addr ${initrdaddr};" \
> +		"else " \
> +			"setenv initrd_addr -;" \
> +		"fi;\0" \
> +	"check_dtb=" \
> +		"if run loaddtb; then " \
> +			"setenv fdt_addr ${fdtaddr};" \
> +		"else " \
> +			"setenv fdt_addr;" \
> +		"fi;\0" \
> +	"kernel_args=" \
> +		"setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
> +		" rootwait ${console} ${opts}\0" \
> +	"boot_fit=" \
> +		"setenv kerneladdr 0x42000000;" \
> +		"setenv kernelname Image.itb;" \
> +		"run loadkernel;" \
> +		"run kernel_args;" \
> +		"bootm ${kerneladdr}#${boardname}\0" \
> +	"boot_uimg=" \
> +		"setenv kerneladdr 0x40007FC0;" \
> +		"setenv kernelname uImage;" \
> +		"run check_dtb;" \
> +		"run check_ramdisk;" \
> +		"run loadkernel;" \
> +		"run kernel_args;" \
> +		"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
> +	"boot_zimg=" \
> +		"setenv kerneladdr 0x40007FC0;" \
> +		"setenv kernelname zImage;" \
> +		"run check_dtb;" \
> +		"run check_ramdisk;" \
> +		"run loadkernel;" \
> +		"run kernel_args;" \
> +		"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \
> +	"autoboot=" \
> +		"if test -e mmc 0 Image.itb; then; " \
> +			"run boot_fit;" \
> +		"elif test -e mmc 0 zImage; then; " \
> +			"run boot_zimg;" \
> +		"elif test -e mmc 0 uImage; then; " \
> +			"run boot_uimg;" \
> +		"fi;\0" \
> +	"console=" CONFIG_DEFAULT_CONSOLE \
> +	"mmcbootdev=0\0" \
> +	"mmcbootpart=1\0" \
> +	"mmcrootdev=0\0" \
> +	"mmcrootpart=2\0" \
> +	"bootdelay=0\0" \
> +	"dfu_alt_info=Please reset the board\0" \
> +	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
> +	"consoleoff=set console console=ram; save; reset\0" \

I think you want to remove these.

Best Regards,
Jaehoon Chung

> +	"initrdname=uInitrd\0" \
> +	"initrdaddr=42000000\0" \
> +	"fdtaddr=40800000\0"
> +
> +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */
> +#undef CONFIG_EXYNOS_TMU
> +#undef CONFIG_TMU_CMD_DTT
> +
> +#ifdef CONFIG_CMD_NET
> +#undef CONFIG_CMD_NET
> +#undef CONFIG_SMC911X
> +#undef CONFIG_CMD_PXE
> +#undef CONFIG_MENU
> +#endif
> +
> +#endif	/* __CONFIG_H */
>