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From: Stefan Roese <sr@denx.de>
To: Huang Shijie <shijie8@gmail.com>
Cc: devicetree@vger.kernel.org,
	Brian Norris <computersforpeace@gmail.com>,
	linux-mtd@lists.infradead.org
Subject: Re: [PATCH] mtd: gpmi: Remove "We support only one NAND chip" from bindings doc
Date: Fri, 28 Nov 2014 08:01:41 +0100	[thread overview]
Message-ID: <54781DD5.5030801@denx.de> (raw)
In-Reply-To: <20141128014832.GA3113@localhost.localdomain>

On 28.11.2014 02:48, Huang Shijie wrote:
> On Thu, Nov 27, 2014 at 03:18:49PM +0100, Stefan Roese wrote:
>> This sentence "We support only one NAND chip now" is not true any more.
>> Multiple chips are supported. So lets remove this sentence to not
>
> The gpmi can only supports one chip. Of course, there are maybe two dies
> in this single chip.

Now I'm a bit confused. The i.MX6 supports 4 chips select signals. And 
isn't "two dies in this single chip" not practically the same as 
connecting 2 (or more) chips (same device) to multiple chip selects of 
the SoC? Where is the difference here?

Thanks,
Stefan

WARNING: multiple messages have this Message-ID (diff)
From: Stefan Roese <sr-ynQEQJNshbs@public.gmane.org>
To: Huang Shijie <shijie8-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Brian Norris
	<computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH] mtd: gpmi: Remove "We support only one NAND chip" from bindings doc
Date: Fri, 28 Nov 2014 08:01:41 +0100	[thread overview]
Message-ID: <54781DD5.5030801@denx.de> (raw)
In-Reply-To: <20141128014832.GA3113-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>

On 28.11.2014 02:48, Huang Shijie wrote:
> On Thu, Nov 27, 2014 at 03:18:49PM +0100, Stefan Roese wrote:
>> This sentence "We support only one NAND chip now" is not true any more.
>> Multiple chips are supported. So lets remove this sentence to not
>
> The gpmi can only supports one chip. Of course, there are maybe two dies
> in this single chip.

Now I'm a bit confused. The i.MX6 supports 4 chips select signals. And 
isn't "two dies in this single chip" not practically the same as 
connecting 2 (or more) chips (same device) to multiple chip selects of 
the SoC? Where is the difference here?

Thanks,
Stefan

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  reply	other threads:[~2014-11-28  7:02 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-27 14:18 [PATCH] mtd: gpmi: Remove "We support only one NAND chip" from bindings doc Stefan Roese
2014-11-27 14:18 ` Stefan Roese
2014-11-28  1:48 ` Huang Shijie
2014-11-28  1:48   ` Huang Shijie
2014-11-28  7:01   ` Stefan Roese [this message]
2014-11-28  7:01     ` Stefan Roese
2014-11-29  2:40     ` Huang Shijie
2014-11-29  2:40       ` Huang Shijie
2014-11-30  6:53       ` Brian Norris
2014-11-30  6:53         ` Brian Norris
2014-11-30 15:42         ` Huang Shijie
2014-11-30 15:42           ` Huang Shijie
2014-12-01  9:58           ` Stefan Roese
2014-12-01  9:58             ` Stefan Roese
2014-12-02  0:38             ` Huang Shijie
2014-12-02  0:38               ` Huang Shijie
2014-12-02  7:28               ` Stefan Roese
2014-12-02  7:28                 ` Stefan Roese
2014-12-03  0:35                 ` Huang Shijie
2014-12-03  0:35                   ` Huang Shijie
2014-12-17  1:17                   ` Brian Norris
2014-12-17  1:17                     ` Brian Norris
2014-12-18  2:45                     ` Brian Norris
2014-12-18  2:45                       ` Brian Norris

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